Recently, there's been a trend toward processors based on the RISC (Reduced Instruction Set Computer) design: Some example RISC processors are the MIPS, SPARC, PowerPC, ARM, and even Intel s 64-bit processor Itanium.

This guidebook provides an accessible and all-encompassing compendium on RISC processors, introducing five RISC processors: MIPS, SPARC, PowerPC, ARM and Itanium. Initial chapters explain the differences between the CISC and RISC designs, and one clearly discusses the RISC design principles. Roughly the second half of the book is dedicated to MIPS assembly language...

Introduces Linux concepts to programmers who are familiar with other operating systems such as Windows XP

Provides comprehensive coverage of the Pentium assembly language

This advanced textbook provides a comprehensive survey of hardware and software architectural principles and methods of computer systems organization and design. It covers both CISC and RISC processors in detail, presenting Pentium, PowerPC, MIPS, SPARC and Itanium. In addition, assembly language programming for both CISC (Pentium) and RISC (MIPS) processors is covered in detail. Numerous assembly language code examples are included to give hands-on experience to students. These examples are not code fragments, but completely working programs that the students can run when they download the...

Multiple processor systems are an important class of parallel systems. Over the years, several architectures have been proposed to build such systems to satisfy the requirements of high performance computing. These architectures span a wide variety of system types. At the low end of the spectrum, we can build a small, shared-memory parallel system with tens of processors. These systems typically use a bus to interconnect the processors and memory. Such systems, for example, are becoming commonplace in high-performance graph- ics workstations. These systems are called uniform memory access...