Memory Organization.- Locality: The 3rd Wall and The Need for Innovation in Parallel Architectures.- Static extraction of memory access profiles for multi-core interference analysis of real-time tasks.- Transparent Resilience for Approximate DRAM.- Heterogeneous Computing.- Automatic Mapping of Parallel Pattern-based Algorithms on Heterogeneous Architectures.- Assessing and Improving the Suitability of Model-Based Design for GPU-Accelerated Railway Control Systems.- DRT: A Lightweight Runtime for Developing Benchmarks for a Dataflow Execution Model.- Instruction Set Transformations.- Performance Gain of a Data Flow Oriented ISA as Replacement for Java Bytecode.- Towards Transparent Dynamic Binary Translation from RISC-V to a CGRA.- Organic Computing.- An Organic Computing System for Automated Testing.- Evaluating a Priority-Based Task Distribution Strategy for an Artificial Hormone System.- Low Power Design.- Streamlining the OpenMP Programming Model on Ultra-Low-Power Multi-Core MCUs.- Energy Efficient Power-Management for Out-of-Order Processors using Cyclic Power-Gating.- VEFRE Workshop.- BCH 2-Bit and 3-Bit Error Correction with Fast Multi-Bit Error Detection.- Evaluating Soft Error Mitigation Trade-offs During Early Design Stages.