Junctionless Field-Effect Transistors: Design, Modeling, and Simulation

ISBN-13: 9781119523536 / Angielski / Twarda / 2019 / 496 str.

Shubham Sahay; Mamidala J. Kumar

Spis treści

Preface xi1 Introduction to Field-Effect Transistors 11.1 Transistor Action 21.2 Metal-Oxide-Semiconductor Field-Effect Transistors 41.3 MOSFET Circuits: The Need for Complementary MOS 91.4 The Need for CMOS Scaling 111.5 Moore's Law 131.6 Koomey's Law 131.7 Challenges in Scaling the MOSFET 131.8 Conclusion 23References 232 Emerging FET Architectures 272.1 Tunnel FETs 282.2 Impact Ionization MOSFET 342.3 Bipolar I-MOS 392.4 Negative Capacitance FETs 412.5 Two-Dimensional FETs 462.6 Nanowire FETs 492.7 Nanotube FETs 512.8 Conclusion 57References 583 Fundamentals of Junctionless Field-Effect Transistors 673.1 Device Structure 693.2 Operation 703.3 Design Parameters 803.4 Parameters that Affect the Performance 823.5 Beyond Silicon JLFETS: Other Materials 1003.6 Challenges 1033.7 Conclusion 110References 1114 Device Architectures to Mitigate Challenges in Junctionless Field-Effect Transistors 1254.1 Junctionless Accumulation-Mode Field-Effect Transistors 1264.2 Realizing Efficient Volume Depletion 1294.3 SOI JLFET with a High-kappa Box 1314.4 Bulk Planar JLFET 1374.5 JLFET with a Nonuniform Doping 1404.6 JLFET with a Step Doping Profile 1444.7 Multigate JLFET 1494.8 JLFET with a High-kappa Spacer 1534.9 JLFET with a Dual Material Gate 1574.10 Conclusion 162References 1625 Gate-Induced Drain Leakage in Junctionless Field-Effect Transistors 1735.1 Hole Accumulation 1745.2 Parasitic BJT Action 1765.3 Impact of BTBT-Induced Parasitic BJT Action on Scaling 1775.4 Impact of Silicon Film Thickness on GIDL 1795.5 Impact of Doping on GIDL 1875.6 Impact of Spacer Design on GIDL 1895.7 Nature of GIDL in Different NWFET Configurations 1905.8 Device Architectures to Mitigate GIDL 1995.9 Conclusion 248References 2496 Impact Ionization in Junctionless Field-Effect Transistors 2556.1 Impact Ionization 2566.2 Floating Body Effects in Silicon-on-Insulator MOSFETs 2566.3 Nature of Impact Ionization in JLFETs 2606.4 Zero Gate Oxide Thickness Coefficient 2636.5 Single Transistor Latch-Up in JLFETs 2666.6 Impact of Body Bias on Impact Ionization in JLFETs 2676.7 Subband Gap Impact Ionization in DGJLFETS with Asymmetric Operation 2686.8 Impact of Gate Misalignment on Impact Ionization in DGJLFETs 2706.9 Spacer Design Guideline from Impact Ionization Perspective 2726.10 Hysteresis and Snapback in JLFETs 2736.11 Impact of Heavy-Ion Irradiation on JLFETs 2756.12 Conclusions 276References 2767 Junctionless Devices Without Any Chemical Doping 2817.1 Charge Plasma Doping 2827.2 Charge Plasma Based p-n Diode 2837.3 Junctionless I-MOS FET 2887.4 Junctionless Tunnel FETs 2907.5 JLTFET on a Highly Doped Silicon Film 2947.6 Bipolar Enhanced JLTFET 2947.7 Junctionless FETS Without Any Chemical Doping 2977.8 Challenges for CPJLFETs 3027.9 Electrostatic Doping Based FETs 3127.10 Conclusions 319References 3198 Modeling Junctionless Field-Effect Transistors 3278.1 Introduction to FET Modeling 3288.2 Surface Potential Modeling of JLFETs 3308.3 Charge-Based Modeling Approach 3518.4 Drain Current Modeling Approach 3558.5 Modeling Short-Channel JLFETs 3658.6 Modeling Quantum Confinement 3728.7 Conclusion 379References 3799 Simulation of JLFETS Using Sentaurus TCAD 3859.1 Introduction to TCAD 3869.2 Tool Flow 3879.3 Sample Input Deck for Long-Channel JLFETS 3919.4 Model Calibration 4079.5 Model Calibration for Short-Channel JLFETs 4099.6 Model Calibration for NWFETS 422References 43610 Conclusion and Perspectives 43910.1 JLFETS As a Label-Free Biosensor 44110.2 JLFETS As Capacitorless DRAM 44310.3 Nanowire Junctionless NAND Flash Memory 44410.4 Junctionless Polysilicon TFTS with a Hybrid Channel 44710.5 JLFETS for 3D Integrated Circuits 44910.6 Summary 450References 451Index 457

O autorze

SHUBHAM SAHAY, PHD, is a Post-Doctoral Research Scholar in the Department of Electrical and Computer Engineering, University of California, Santa Barbara. He has authored several peer-reviewed journal articles on topics including semiconductor device design and modeling and unconventional applications of emerging non-volatile memories.MAMIDALA JAGADESH KUMAR, PHD, is a Professor at the Indian Institute of Technology, New Delhi and Vice-Chancellor of Jawaharlal Nehru University, New Delhi. He is Editor-in-Chief of IETE Technical Review and has widely published in the area of Micro/Nanoelectronics.