Architectural Optimizations in Multi-Core Processors

ISBN-13: 9783639101577 / Angielski / Miękka / 2008 / 144 str.

Sevin Fide

Opis

The quest for greater computational power is never-ending. Recently, the architectural trend has shifted from improving single-threaded application performance to improving multi-threaded application performance. Thus, multi-core processors have been increasingly popular. To achieve concurrent execution of threads on multi-core processors, applications must be explicitly restructured to exploit parallelism, either by programmers or compilers. However, conventional parallel programming models may introduce overhead due to synchronization and communications among threads in multi-threaded applications. This book presents three architectural optimizations to improve thread-based synchronization and communications support in multi-core processors. Register-Based Synchronization (RBS) uses hardware registers efficiently to provide synchronization support in multi-core processors. Prepushing is a software controlled data forwarding technique to provide communications support in multi-core processors. Software Controlled Eviction (SCE) improves shared cache communications by placing shared data in shared caches."

O autorze

Sevin Fide was born in Cyprus in 1981. She graduated from Eastern
Mediterranean University in 2002 with a degree in Computer
Engineering. She received M.S. and Ph.D. degrees in Electrical
and Computer Engineering from the University of California,
Irvine in 2004 and 2008, respectively. She is currently a
graphics software engineer at Intel.