Yield-Aware Analog IC Design and Optimization in Nanometer-Scale Technologies

ISBN-13: 9783030415389 / Angielski / Miękka / 2021 / 237 str.

António Manuel Lourenço Canelas; Jorge Manuel Correia Guilherme; Nuno Cavaco Gomes Horta

Spis treści

1. Introduction

2. Analog IC Sizing Background

3. Yield Estimation Techniques Related Work

4. Monte Carlo-Based Yield Estimation New Methodology

5. AIDA-C Variation-Aware Circuit Synthesis Tool

6. Tests & Results

7. Conclusion and Future Work

Index

O autorze

António Canelas received the B.Sc., M.Sc. and PhD degrees in electrical engineering from Instituto Superior Técnico (IST), University of Lisbon, Portugal, in 2010, 2012 and 2019, respectively. In 2011, he had a research position at the Instituto de Telecomunicações, working on time series analysis and pattern discovery. He is now a post-doctoral researcher at the same institution, working in the area of analog and mixed-signal IC design automation and evolutionary computation techniques.

Jorge Guilherme has a PhD (2003), a MSc (1994) and an Electrical and Computer Engineer (1989) degree from Instituto Superior Técnico, University of Lisbon, Portugal, in the area of microelectronics. Has worked in the microelectronics area since 1990 and has published more than 60 papers in the field. He is a professor at the Instituto Politecnico Tomar since 1996. He is with the Instituto de Telecomunicações since 2004, in the Integrated Circuits Group.

Nuno Horta received the Licenciado, MSc, PhD and Habilitation degrees in Electrical and Computer Engineer from Instituto Superior Técnico (IST), University of Lisbon, Portugal, in 1989, 1992, 1997 and 2014, respectively. In March 1998, he joined the IST Electrical and Computer Engineering Department where he is currently an Associate Professor with Habilitation. Since 1998, he is, also, with Instituto de Telecomunicações, where he is the head of the Integrated Circuits Group. He has supervised more than 100 post-graduation works between MSc and PhD theses. He has authored or co-authored more than 150 publications as books, book chapters, international journals papers and conferences papers. He has also participated as researcher or coordinator in several National and European R&D projects. He was General Chair of AACD 2014, PRIME 2016 and SMACD 2016 and was member of the organizing and technical program committees of several other conferences, e.g., IEEE ISCAS, IEEE LASCAS, DATE, NGCAS, etc. He is Associated Editor of Integration, The VLSI Journal, from Elsevier, and usually acts as reviewer of several prestigious publications, e.g., IEEE TCAD, IEEE TEC, IEEE TCAS, ESWA, ASC, etc. His research interests are mainly in analog and mixed-signal IC design, analog IC design automation, soft computing and data science.

Blurb

This book presents a new methodology with reduced time impact to address the problem of analog integrated circuit (IC) yield estimation by means of Monte Carlo (MC) analysis, inside an optimization loop of a population-based algorithm. The low time impact on the overall optimization processes enables IC designers to perform yield optimization with the most accurate yield estimation method, MC simulations using foundry statistical device models considering local and global variations.  The methodology described by the authors delivers on average a reduction of 89% in the total number of MC simulations, when compared to the exhaustive MC analysis over the full population.  In addition to describing a newly developed yield estimation technique, the authors also provide detailed background on automatic analog IC sizing and optimization.

• Describes a new yield estimation methodology to reduce the time impact caused by Monte Carlo simulations, enabling its adoption in analog integrated circuits sizing and optimization processes with population-based algorithms;
• Enables designers to reduce the number of redesign iterations, by considering the robustness of solutions at early stages of the analog IC design flow;
• Includes detailed background on automatic analog IC sizing and optimization.