Verification by Error Modeling: Using Testing Techniques in Hardware Verification

ISBN-13: 9781441954022 / Angielski / Miękka / 2010 / 216 str.

Katarzyna Radecka; Zeljko Zilic

Opis

1. DESIGN FLOW Integrated circuit (IC) complexity is steadily increasing. ICs incorporating hundreds of millions of transistors, mega-bit memories, complicated pipelined structures, etc., are now in high demand. For example, Intel Itanium II processor contains more than 200 million transistors, including a 3 MB third level cache. A billion transistor IC was said to be imminently doable by Intel fellow J. Crawford at Microprocessor Forum in October 2002 40]. Obviously, designing such complex circuits poses real challenges to engineers. Certainly, no relief comes from the competitive marketplace, with increasing demands for a very narrow window of time (time-to-market) in engineering a ready product. Therefore, a systematic and well-structured approach to designing ICs is a must. Although there are no widely adhered standards for a design flow, most companies have their own established practices, which they follow closely for in-house design processes. In general, however, a typical product cycle includes few milestones. An idea for a new product starts usually from an - depth market analysis of customer needs. Once a window of opportunity is found, product requirements are carefully specified. Ideally, these parameters would not change during the design process. In practice, initial phases of preparing a design specification are susceptible to potential errors, as it is very difficult to grasp all the details in a complex design."

Recenzje

From the reviews:

"This monograph presents, as its main contribution, methods to gain more confidence in verification by simulation. ... The methods presented in this book may be suitable to verify gate level circuits which may have small modifications after automatic optimization or some manual interaction." (Reiner Kolla, Zentralblatt MATH, Vol. 1049 (24), 2004)

Spis treści

1: Introduction. 1. Design flow. 2. Verification - approaches and problems. 3. Book objectives. 2: Boolean function representations. 1. Background - function representations. 2. Decision diagrams. 3. Spectral representations. 4. Arithmetic transform. 3: Don't cares and their calculation. 1. Incompletely specified Boolean functions. 2. Using don't cares for redundancy identification. 4: Testing. 1. Introduction. 2. Fault list reduction. 3. Overview of simulators. 4. Fault simulators. 5. Deterministic vector generation - ATPG. 6. Conclusions. 5: Design error models. 1. Introduction. 2. Design errors. 3. Explicit design error models. 4. Implicit error model precursors. 5. Additive implicit error model. 6. Design error detection and correction. 7. Conclusions. 6: Design verification by AT. 1. Introduction. 2. Detecting small AT errors. 3. Bounding error by Walsh transform. 4. Experimental results. 5. Conclusions. 7: Identifying redundant gate and wire replacements. 1. Introduction. 2. Gate replacement faults. 3. Redundancy detection by don't cares. 4.Exact redundant fault identification. 5. Identifying redundant wire replacements. 6. Exact wire redundancy identification. 7. I/O port replacement detection. 8. Experimental results. 9. Conclusions. Conclusions and furtherwork. 1. Conclusions. 2. Future work. Appendices. References. Index.