Verification Methodology Manual for Systemverilog

ISBN-13: 9780387255385 / Angielski / Twarda / 2005 / 503 str.

Janick Bergeron; Eduard Cerny; Alan Hunter

Opis

Offers users the first resource guide that combines both the methodology and basics of SystemVerilog Addresses how all these pieces fit together and how they should be used to verify complex chips rapidly and thoroughly. Unique in its broad coverage of SystemVerilog, advanced functional verification, and the combination of the two.

Spis treści

Verification Planning.- Assertions.- Testbench Infrastructure.- Stimulus and Response.- Coverage-Driven Verification.- Assertions for Formal Tools.- System-Level Verification.- Processor Integration Verification.

O autorze

Janick Bergeron is a Scientist at Synopsys, Inc. He is the author of the best-selling book Writing Testbenches: Functional Verification of HDL Models and the moderator of the Verification Guild. Prior to joining Synopsys, Janick worked on verification methodology at Qualis Design Corporation and Bell-Northern Research. He holds a Masters degree in Electrical Engineering from the University of Waterloo, a Bachelor of Science degree in Engineering from the Université du Québec, and an MBA degree granted through the University of Oregon.

Eduard Cerny is a Principal Engineer, R&D, in the Verification Group at Synopsys, Inc. He joined Synopsys in 2001 after 25 years in academia, as Professor of Computer Science at the Université de Montréal. Eduard has a B.Sc. in Electrical Engineering from Loyola College in Montreal, Canada, and a M.Eng. and Ph.D. in Electrical Engineering from McGill University in Montreal, Canada. His interests have been in design, verification and test of hardware, and he is author of many articles in these areas.

Alan Hunter, BEng(Hons), MSc, is the Design Verification Methodology Programme manager at ARM Ltd. and is leading the design verification methodology work for ARM worldwide. This work covers all areas from CPU design verification through systems and system component design verification. His main areas of interest include optimizing design verification efficiency and quality, formal methods, and determinism in the design verification flow. Prior to joining ARM, Alan worked for a small formal verification company specializing in property and equivalence checking.

Andy Nightingale, BEng(Hons), MBCS CITP, is a consultant engineer at ARM Ltd and has led the SoC Verification group in ARM’s Cambridge and Sheffield design centers for the past four years. The group covers ARM PrimeXSys platforms and PrimeCell development, including advanced AXI- and AHB-based system backplane components such as bus interconnects and high-performance memory controllers. Prior to working at ARM, Andy worked as a real-time embedded systems engineer for a successful scientific instrument company, primarily serving the semiconductor industry.