VLSI Design

ISBN-13: 9780849318764 / Angielski / Twarda / 2000 / 424 str.

M. Michael Vai

Opis

Very Large Scale Integration (VLSI) has become a necessity rather than a specialization for electrical and computer engineers. This unique t ext provides a comprehensive study of the subject, covering VLSI from basic design techniques to working principles of physical design autom ation tools to leading edge application-specific array processors. Beg inning with CMOS design, the author describes VLSI design from the vie wpoint of a digital circuit engineer. He develops physical pictures fo r CMOS circuits and demonstrates the top-down design methodology using two design projects - a microprocessor and a field programmable gate array. The author then discusses VLSI testing and dedicates an entire chapter to the working principles, strengths, and weaknesses of ubiqui tous physical design tools. Finally, he unveils the frontiers of VLSI. He emphasizes its use as a tool to develop innovative algorithms and architecture to solve previously intractable problems.

Spis treści

PREFACE
INTRODUCTION
VLSI Design Methodology
VLSI Design ¾ An Overview
CMOS LOGIC CIRCUITS
nMOS Switch Model
pMOS Switch Model
CMOS Inverter
CMOS Logic Structures
Complementary Logic
Pass-Transistor/Transmission-Gate Logic
IC LAYOUT AND FABRICATION
CMOS IC Fabrication
CMOS Design Rules
Layout Examples
CMOS CIRCUIT CHARACTERIZATION
MOSFET Theory
Voltage Transfer Characteristic
Circuit-Level Simulation
Improved MOSFET Switch Model
Resistance/Capacitance Estimation
RC Timing Model
Transistor Sizing
t-Model
Driving Large Loads
Power Dissipation
Latch-Up
SEQUENTIAL LOGIC CIRCUITS
General Structure
Asynchronous Sequential Logic Circuits
D-Latch
D-Flip-Flop
One-Phase Clock Systems
Two-Phase, Non-Overlapping Clock Systems
Clock Distribution
Sequential Circuit Design
ALTERNATIVE LOGIC STRUCTURES
Complementary Logic Circuits
Pass-Transistor/Transmission-Gate Logic
Pseudo-nMOS Logic
Programmable Logic Array
Dynamic CMOS Logic
Domino Logic
Dynamic Memory Elements
BiCMOS Logic Circuits
SUB-SYSTEM DESIGN
Adders
Full Adder Tree
Parallel Multipliers
Read-Only Memory
Random Access Memory
CHIP DESIGN
Microprocessor Design Project
Field Programmable Gate Array
TESTING
Fault Models
Test Generation (Stuck-At Faults)
Path Sensitization
D-Algorithm
Test Generation for Other Fault Models
Test Generation Example
Sequential Circuit Testing
Design-for-Testability
Built-In Self-Test
PHYSICAL DESIGN AUTOMATION
Layout Generators and Editors
Placement and Routing
Floorplanning and Placement
Routing
PARALLEL STRUCTURES
Parallel Architectures
Interconnection Networks
Pipelining
Pipeline Scheduling
Parallel Algorithms

Each chapter also includes sections titled: Summary, To Probe Further, and Problems.

O autorze

Vai, M. Michael