VLSI Architectures for Modern Error-Correcting Codes

ISBN-13: 9780367738037 / Angielski / Miękka / 2020 / 410 str.

Xinmiao Zhang

Opis

This book discusses practical implementation architectures for modern error-correcting codes, providing details for every functional block as well as the overall decoder architecture. Particular emphases are placed on hard- and soft-decision Reed-Solomon (RS) and Bose-Chaudhuri-Hocquenghem (BCH) codes, and binary and non-binary low-density parit

Spis treści

Finite Field Arithmetic. VLSI Architecture Design Fundamentals. Root Computations for Polynomials Over Finite Fields. Reed-Solomon Encoder and Hard-Decision Decoder Architectures. Algebraic Soft-Decision Reed-Solomon Decoder Architectures. Interpolation-Based Chase and Generalized Minimum Distance Decoders. BCH Encoder and Decoder Architectures. Binary LDPC Codes and Decoder Architectures. Non-Binary LDPC Decoder Architectures.

O autorze

Xinmiao Zhang received her Ph.D in electrical engineering from the University of Minnesota, Twin Cities, USA. She is currently an Associate Professor in the Department of Electrical and Computer Engineering at The Ohio State University. Previously, she was a Timothy E. and Allison L. Schroeder Associate Professor at Case Western Reserve University, Cleveland, Ohio. Between her academic positions, she continued her research on error-correcting codes at SanDisk/Western Digital Corporation. She has also been a visiting professor at Qualcomm and spent her sabbatical leave at the University of Washington, Seattle, USA. Her research focuses on VLSI architecture design for communications, digital signal processing, and cryptography. She is a recipient of the National Science Foundation Faculty Early Career Development (CAREER) Award.