Turbo Codes: Desirable and Designable

ISBN-13: 9781461350965 / Angielski / Miękka / 2012 / 150 str.

Alexandre Giulietti; Bruno Bougard; Liesbet Van Der Perre

Opis

Turbo Codes: Desirable and Designable introduces the basics of turbo codes in their different flavors (more specifically, parallel concatenated convolutional turbo codes and block turbo codes). Through the application of systemic design methodology that considers data transfer and storage as top priority candidates for optimization, the authors show how turbo codes can be implemented and the attractive performance results that can be achieved in throughput, latency and energy consumption. These solutions and results make turbo-codes close competitors to traditional coding scheme such as convolutional codes or algebraic codes.

Finally, a real-life prototype of parallel concatenated convolutional (turbo-) codes is presented. A complete turbo codes ASIC data-flow is described together with on-board power, speed and coding gain measurements that demonstrate the effectiveness of the proposed solution.

Spis treści

1: Turbo CodesIntroducing the communication problem they solve, and the implementation problem they create.- 1.1. A communication and Microelectronics perspective.- 1.1.1 Scientific fathers recalled: Shannon and Shockley.- 1.1.2 Channel coding: from simple engines to turbo.- 1.1.3 IC revolution: from transistors to 4G radios.- 1.1.4 The implementation problem and goals.- 1.2. Turbo codes: desirable channel coding solutions.- 1.2.1 Channel coding: an essential ingredient in digital communication systems.- 1.2.2 Block and Convolutional Channel Codes: the basics.- 1.2.3 Concatenated codes.- 1.2.4 Parallel concatenated convolutional (turbo) codes.- 1.2.5 Decoding parallel concatenated Turbo codes.- 1.2.6 Serially concatenated block codes.- 1.3 Conclusions.- 1.4 References.- 2: Design Methodology: The Strategic PlanGetting turbo-codes implemented at maximum performance/cost.- 2.1 Introduction.- 2.2 Algorithmic exploration.- 2.3 Data Transfer and Storage Exploration.- 2.4 From architecture to silicon integration.- 2.5 Conclusions.- 2.6 References.- 3: Conquering the MapRemoving the main bottleneck of convolutional turbo decoders.- 3.1 Introduction.- 3.2 The MAP decoding algorithm for convolutional turbo codes.- 3.3 Simplification of the MAP algorithm: log-max MAP.- 3.3.1 The log-max MAP algorithm.- 3.4 Trellis termination in convolutional turbo codes.- 3.4.1 No termination.- 3.4.2 Single termination.- 3.4.3 Double termination.- 3.5 MAP architecture definition: systematic approach.- 3.5.1 MAP bottlenecks.- 3.5.2 Data Flow and Loop Transformations.- 3.5.3 Storage Cycle Budget Distribution.- 3.5.4 Memory organization.- 3.6 Conclusions.- 3.7 References.- 4: Demystifying the Fang-Buda AlgorithmBoosting the block turbo decoding.- 4.1. Introduction.- 4.2. Soft decoding of algebraic codes.- 4.2.1 Maximum likelihood decoding of block codes.- 4.2.2 The Chase algorithm.- 4.2.3 The Fang-Buda Algorithm (FBA).- 4.3. FBA Optimization and Architecture Derivation.- 4.3.1 Data Type Refinement.- 4.3.2 Data and control flow transformations.- 4.3.3 Data Reuse Decision and Storage Cycle Budget Distribution.- 4.3.4 Memory allocation and assignment.- 4.4. FBA-based BTC decoder performance.- 4.5. Conclusions.- 4.6. References.- 5: Mastering the InterleaverDivide and Conquer.- 5.1. Introduction.- 5.2. Basic elements of the interleaver.- 5.3. Collision-free interleavers.- 5.4. Case study: the 3GPP interleaver and a 3GPP collision-free interleaver.- 5.5. Optimized scheduling for turbo decoding: collision-free interleaving and deinterleaving.- 5.6. References.- 6: T@MPO CodecFrom theory to real life silicon.- 6.1. Introduction.- 6.2. Positioning oneself in the optimal performance-speed-cost space.- 6.3. Design flow.- 6.4. Decoder final architecture.- 6.5. Synthesis results.- 6.6. Measurements results.- 6.7. T@MPO features.- 6.8. References.- Abbreviations list.- Symbol list.