The Verilog Pli Handbook: A User's Guide and Comprehensive Reference on the Verilog Programming Language Interface

ISBN-13: 9781461372790 / Angielski / Miękka / 2012 / 785 str.

Stuart Sutherland

Opis

by Maq Mannan President and CEO, DSM Technologies Chairman of the IEEE 1364 Verilog Standards Group Past Chairman of Open Verilog International One of the major strengths of the Verilog language is the Programming Language Interface (PLI), which allows users and Verilog application developers to infinitely extend the capabilities of the Verilog language and the Verilog simulator. In fact, the overwhelming success of the Verilog language can be partly attributed to the exist- ence of its PLI. Using the PLI, add-on products, such as graphical waveform displays or pre and post simulation analysis tools, can be easily developed. These products can then be used with any Verilog simulator that supports the Verilog PLI. This ability to create third- party add-on products for Verilog simulators has created new markets and provided the Verilog user base with multiple sources of software tools. Hardware design engineers can, and should, use the Verilog PLI to customize their Verilog simulation environment. A Company that designs graphics chips, for exam- ple, may wish to see the simulation results of a new design in some custom graphical display. The Verilog PLI makes it possible, and even trivial, to integrate custom soft- ware, such as a graphical display program, into a Verilog simulator. The simulation results can then dynamically be displayed in the custom format during simulation. And, if the company uses Verilog simulators from mUltiple simulator vendors, this integrated graphical display will work with all the simulators.

Spis treści

List of Examples. Foreword. Acknowledgments. Introduction. Part One: The VPI Portion of the Verilog PLO Standard. 1. Creating PLI Applications Using VPI Routines. 2. Interfacing VPI based PLI Applications to Verilog Simulators. 3. How to Use the VPI Routines. 4. Details about the VPI Routine Library. 5. Reading and Modifying Values Using VPI Routines. 6. Synchronizing to Verilog Simulations Using VPI Callbacks. 7. Interfacing to C Models Using VPI Routines. Part Two: The TF/ACC Portion of the Verilog PLI Standard. 8. Creating PLI Applications Using TF and ACC Routines. 9. Interfacing TF/ACC PLI Applications to Verilog Simulators. 10. How to Use the TF Routines. 11. Reading and Writing Values Using TF Routines. 12. Synchronizing to Verilog Simulations Using Misctf Routines. 13. Interfacing to C Models Using TF Routines. 14. How to Use the ACC Routines. 15. Details on the ACC Routine Library. 16. Reading and Modifying Values Using ACC Routines. 17. Synchronizing to Simulations Using the Value Change Link. 18. Interfacing to C Models Using ACC Routines. Appendices: A. Linking PLI Applications to Verilog Simulators. B. The IEEE 1364-1995 VPI Routine Library. C. The IEEE 1364-1995 TF Routine Library. D. The IEEE 1364-1995 ACC Routine Library. Index.

O autorze

Mr. Stuart Sutherland is a member of the IEEE Verilog standards committee, where he is co-chair of the PLI standards task force and technical editor for the PLI sections of the IEEE 1364 Verilog Language Reference Manual. 

Mr. Sutherland has more than 14 years of experience in hardware design and over ten years of experience with Verilog. He is the founder of Sutherland HDL Inc., located in Portland Oregon. Sutherland HDL provides expert Verilog HDL and Verilog PLI design services, including training, modeling, design verification and software tool evaluation. Verilog training is one of the specialties of Sutherland HDL. Prior to founding Sutherland HDL in 1992, Mr. Sutherland was as an engineer at Sanders Display Products Division in New Hampshire, where he worked on high speed graphics systems for the defense industry. In 1988, he became a senior applications engineer for Gateway Design Automation, the founding company of Verilog. At Gateway, which was acquired by Cadence Design Systems in 1989, Mr. Sutherland specialized in training and support for logic simulation, timing analysis, fault simulation, and the Verilog PLI. Mr. Sutherland has also worked closely with several EDA vendors to specify, test and bring to market Verilog simulation products. 

Mr. Sutherland holds a Bachelor of Science in Computer Science, with an emphasis in Electronic Engineering Technology, from Weber State University (Ogden, Utah) and Franklin Pierce College (Nashua, New Hampshire). He has taught Verilog engineering courses at the University of California, Santa Cruz (Santa Clara extension), and has authored the popular "Verilog HDL Quick Reference Guide" and "Verilog PU Quick Reference Guide". He has presented tutorials and papers at the International Verilog Conference and at the International Cadence User's Group Conference, and has won awards for best speaker and best tutorial.