The Esd Handbook

ISBN-13: 9781119965176 / Angielski / Twarda / 2021 / 1168 str.

Steven H. Voldman

Spis treści

About the Author xxxviiAcknowledgements xxxix1 ESD, EOS, EMI, EMC, and Latchup 11.1 Electrostatic Discharge (ESD) 11.2 Human Body Model (HBM) 21.3 Machine Model (MM) 31.4 Cassette Model 31.5 Charged Device Model (CDM) 41.6 Transmission Line Pulse (TLP) 51.7 Very Fast Transmission Line Pulse (VF-TLP) 81.8 Electrical Overstress (EOS) 81.9 Electrical Overstress (EOS) 81.10 EOS Sources - Lightning 91.11 EOS Sources - Electromagnetic Pulse (EMP) 91.12 EOS Sources - Machinery 101.13 EOS Sources - Power Distribution 101.14 EOS Sources - Switches, Relays, and Coils 101.15 EOS Design Flow and Product Definition 101.16 EOS Sources - Design Issues 111.17 Electromagnetic Interference (EMI) 121.18 Electromagnetic Compatibility (EMC) 131.19 Latchup 13Questions and Answers 141.20 Summary and Closing Comments 15References 152 ESD in Manufacturing 212.1 Flooring 212.2 Work Surfaces 212.3 Garments 222.4 Wrist Straps 222.5 Shoes - Footwear 222.6 Ionization 232.7 Clean Rooms 242.8 Carts 262.9 Shipping Tubes 262.10 Trays 272.11 Measurements 272.12 Verification 282.13 Audit 282.14 Triboelectric Charging - How Does it Happen? 292.15 Conductors, Semiconductors, and Insulators 302.16 Static Dissipative Materials 302.17 ESD and Materials 312.18 Electrification and Coulomb's Law 312.19 Electromagnetism and Electrodynamics 332.20 Electrical Breakdown 332.21 Electro-Quasistatics and Magnetoquasistatics 362.22 Electrodynamics and Maxwell's Equations 362.23 Electrostatic Discharge (ESD) 362.24 Electromagnetic Compatibility (EMC) 372.25 Electromagnetic Interference (EMI) 372.26 Fundamentals of Manufacturing and Electrostatics 372.27 Materials, Tooling, Human Factors, and Electrostatic Discharge 382.28 Materials and Human-induced Electric Fields 392.29 Manufacturing Environment and Tooling 392.30 Manufacturing Equipment and ESD Manufacturing Problems 392.31 Manufacturing Materials 392.32 Measurement and Test Equipment 402.33 Manufacturing Testing for Compliance 412.34 Grounding and Bonding Systems 422.35 Work Surfaces 422.36 Wrist Straps 432.37 Constant Monitors 432.38 Footwear 432.39 Floors 442.40 Personnel Grounding with Garments 442.41 Garments 442.42 Air Ionization 442.43 Seating 452.44 Packaging and Shipping 462.45 Trays 462.46 ESD Identification 462.47 ESD Program Auditing 462.48 ESD On-Chip Protection 472.49 ESD, EOS, EMI, EMC, and Latchup 472.50 Manufacturing Electrical Overstress (EOS) 482.51 EMI 502.52 EMC 502.53 Summary and Closing Comments 50References 503 ESD Standards 553.1 Factory - Flooring 553.2 Factory - Resistance Measurement of Materials 563.3 JEDEC 583.4 International Electro-Technical Commission (IEC) 593.5 IEEE 593.6 Department of Defense (DOD) 593.7 Military Standards 593.8 SAE 603.9 Summary and Closing Comments 60Questions and Answers 60References 614 ESD Testing 654.1 Electrostatic Discharge (ESD) Testing 654.2 ESD Models 654.3 HBM Test System 694.4 HBM Two-pin Test System 694.5 Machine Model (MM) 694.6 Small Charge Model (SCM) 704.7 Small Charge Model Source 714.8 CDM Pulse Waveform 724.9 HMM Equivalent Circuit 774.10 HMM Test Equipment 774.11 HMM Test Configuration 784.12 HMM Fixture Board 784.13 Transmission Line Pulse (TLP) 824.14 TLP Test Systems 844.15 IEC 61000-4-2 874.16 Equivalent Circuit 894.17 Test Equipment 894.18 Cable Discharge Event (CDE) 904.19 CDE Pulse Waveform 934.20 Equivalent Circuit 934.21 Commercial Test Systems 944.22 Systems Electromagnetic Interference (EMI) 954.23 Electromagnetic Compatibility (EMC) 954.24 Electrical Overstress (EOS) 954.25 Latchup 954.26 Electrical Overstress (EOS) 954.27 EOS Sources - Lightning 964.28 EOS Sources - Electromagnetic Pulse (EMP) 974.29 Electromagnetic Compatibility 974.30 Summary and Closing Comments 100References 1005 ESD Device Physics 1175.1 Electro-thermal Instability 1175.2 Stable System 1185.3 Unstable System 1185.4 Differential Relation of Voltage and Current 1205.5 Time Constant Hierarchy 1215.6 Thermal Physics Time Constants 1215.7 Adiabatic, Thermal Diffusion Time Scale and Steady State 1215.8 Electro-quasistatic and Magnetoquasistatics 1225.9 Electrical Instability 1245.10 Thermal Physics Time Constants 1255.11 Adiabatic, Thermal Diffusion Time Scale and Steady State 1265.12 Electrical Instability and Breakdown 1265.13 Spatial Instability and Electro-thermal Current Constriction 1275.14 Equipotential Surface 1275.15 Heat Flow 1285.16 Conservation of Heat 1285.17 Electric Potential and Temperature Gradient 1285.18 Electric Energy, Resistivity, and Thermal Conductivity 1295.19 Breakdown 1315.20 Electron Current Continuity Relationship 1365.21 Air Breakdown and Peak Currents 1385.22 Electro-thermal Instability 1395.23 Mathematical Methods - Green's Function and Method of Images 1415.24 Mathematical Methods - Green's Function and Method of Images 1435.25 Mathematical Methods - Integral Transforms of the Heat Conduction Equation 1485.26 Flux Potential Transfer Relations Matrix Methodology 1525.27 Heat Equation Variable Conductivity 1545.28 Mathematical Methods - Boltzmann Transformation 1565.29 Mathematical Methods - The Duhamel Formulation 1585.30 Spherical Source Tasca Model 1605.31 Wunsch-Bell Model 1635.32 The Smith and Littau Model 1665.33 The Arkihpov-Astvatsaturyan-Godovosyn-Rudenko Model 1685.34 The Vlasov-Sinkevitch Model 1695.35 The Dwyer, Franklin and Campbell Model 1695.36 Negative Differential Resistor and Resistor Ballasting 1745.37 Ash Model - Nonlinear Failure Power Thresholds 1765.38 Statistical Models for ESD Prediction 1785.39 Summary and Closing Comments 180References 1806 ESD Events and Protection Circuits 1896.1 Human Body Model (HBM) 1896.2 Machine Model (MM) 1916.3 Charged Device Model 1936.4 Human Metal Model (HMM) 1976.5 IEC 61000-4-2 History 2046.6 IEC 61000-4-5 2096.7 Cable Discharge Event (CDE) 2136.8 CDM Scope 215References 2197 ESD Failure Mechanism 2357.1 Tables of CMOS ESD Failure Mechanisms 2357.2 LOCOS Isolation-Defined CMOS 2357.3 LOCOS-bound Thick Oxide MOSFET 2417.4 LOCOS-Bound Structures 2427.5 Shallow Trench Isolation (STI) 2457.6 STI Pull-down ESD Failure Mechanism 2457.7 STI Pull-Down and Gate Wrap-Around 2467.8 MOSFETs 2477.9 LOCOS-bound Thick Oxide MOSFET 2527.10 Bipolar Transistor Devices 2547.11 Silicide Blocked N-diffusion Resistors 2597.12 Silicon Germanium ESD Failure Mechanisms 2597.13 Silicon Germanium Carbon ESD Failure Mechanisms 2597.14 Gallium Arsenide Technology ESD Failure Mechanisms 2607.15 Indium Gallium Arsenide ESD Failure Mechanisms 2617.16 Micro Electromechanical (MEM) Systems 2637.17 Micro-mirror Array Failures 2657.18 EOS Bond Pad and Interconnect Failure 2697.19 Summary and Closing Comments 272References 2738 ESD Design Synthesis 2818.1 ESD Design Synthesis and Architecture Flow 2818.2 ESD Design - the Signal Path and the Alternate Current Path 2878.3 ESD Electrical Circuit and Schematic Architecture Concepts 2898.4 The Ideal ESD Network 2898.5 Mapping Semiconductor Chips and ESD Designs 2938.6 Mapping across Semiconductor Fabricators 2948.7 ESD Design Mapping across Technology Generations 2958.8 ESD Networks, Sequencing, and Chip Architecture 3068.9 ESD Layout and Floorplan-related Concepts 3148.10 ESD Architecture and Floor-planning 3238.11 Digital and Analog CMOS Architecture 3478.12 Digital and Analog Floorplan - Placement of Analog Circuits 3488.13 Mixed-signal Architecture - Digital, Analog, and RF Architecture 3508.14 Summary and Closing Comments 351Questions 351References 3529 On-chip ESD Protection Circuits - Input Circuitry 3639.1 Receivers and ESD 3639.2 Receivers and Receiver Delay Time 3639.3 ESD Loading Effect on Receiver Performance 3649.4 Receivers and HBM 3659.5 Receivers and CDM 3669.6 Receivers and Receiver Evolution 3689.7 Receiver Circuits with Half-pass Transmission Gate 3689.8 Receiver with Full-pass Transmission Gate 3719.9 Receiver, Half-pass Transmission Gate, and Keeper Network 3739.10 Receiver, Half-pass Transmission Gate, and the Modified Keeper Network 3779.11 Receiver Circuits with Pseudo-zero VT Half-pass Transmission Gates 3799.12 Receiver with Zero VT Transmission Gate 3819.13 Receiver Circuits with Bleed Transistors 3839.14 Receiver Circuits with Test Functions 3849.15 Receiver with Schmitt Trigger Feedback Network 3859.16 Bipolar Transistor Receivers 3899.17 CMOS Differential Receiver with Analog Layout Concepts 3979.18 CMOS Differential Receiver Capacitance Loading 3989.19 CMOS Differential Receiver ESD Mismatch 3989.20 Analog Differential Pair ESD Signal Pin Matching with CommonWell Layout 4009.21 Analog Differential Pair Common Centroid Design Layout - Signal-Pin to Signal-Pin and Parasitic ESD Elements 4039.22 Off-chip Drivers (OCD) 4059.23 Off-chip Driver I/O Standards and ESD 4079.24 Off-chip Driver (OCD) ESD Design Basics 4089.25 Off-chip Drivers (OCD): Mixed Voltage Interface 4149.26 Off-chip Drivers (OCD): Self-bias Well OCD Networks 4149.27 Self-bias Well Off-chip Driver (OCD) Networks 4159.28 ESD Protection Networks for Self-bias Well OCD Networks 4179.29 Programmable Impedance Off-chip Driver (OCD) Network 4189.30 ESD Input Protection Networks for Programmable Impedance Off-chip Drivers 4229.31 Universal Off-chip Drivers 4239.32 Gate Array Off-chip Driver Design 4239.33 Gate Array OCD Design - Impedance Matching of Unused Elements 4259.34 OCD ESD Design - Power Rails Over Multi-finger MOSFETs 4269.35 Off-chip Driver: Gate-modulated MOSFET ESD Network 4279.36 Off-chip Driver Simplified Gate Modulated Network 4289.37 Off-chip Drivers ESD Design: Integration of Coupling and Ballasting Techniques 4289.38 Ballasting and Coupling 4299.39 MOSFET Source-initiated Gate-bootstrapped Resistor Ballasted Multi-finger MOSFET with Diode 4299.40 MOSFET Source-initiated Gate-bootstrapped Resistor Ballasted Multi-finger MOSFET with a MOSFET 4309.41 Gate-coupled Domino Resistor-ballasted MOSFET 4319.42 Substrate-modulated Resistor Ballasted MOSFET 4339.43 Summary and Closing Comments 434Problems 435References 43710 On-Chip ESD Protection Circuits - ESD Power Clamps 44110.1 ESD Power Clamps 44110.2 ESD Power Clamp Design Practices 44110.3 Current Loops 44210.4 Impedance 44210.5 Segmentation 44310.6 Voltage Limitations 44310.7 Latchup 44310.8 ESD Power Clamp Circuits 44410.9 Classification of ESD Power Clamps 44410.10 Master-Slave ESD Power Clamps 44510.11 Trigger Networks 44510.12 ESD Power Clamp Characteristics and Issues 44510.13 Design Synthesis of ESD Power Clamp - Key Design Parameters 44610.14 Design Synthesis of ESD Power Clamps Trigger Networks 44610.15 Transient Response Frequency Trigger Element and the ESD Frequency Window 44610.16 ESD Power Clamp Frequency Design Window 44710.17 Design Synthesis of ESD Power Clamp - Voltage Triggered ESD Trigger Elements 44810.18 Design Synthesis of ESD Power Clamp - The ESD Power Clamp Shunting Element 44910.19 ESD Power Clamp Trigger Condition vs. Shunt Failure 45010.20 ESD Clamp Element - Width Scaling 45010.21 ESD Clamp Element - On-resistance 45010.22 ESD Clamp Element - Safe Operating Area (SOA) 45110.23 ESD Power Clamp Issues 45110.24 ESD Power Clamp Issues - Power-up and Power-down 45110.25 ESD Power Clamp Issues - False Triggering 45210.26 ESD Power Clamp Issues - Pre-charging 45210.27 ESD Power Clamp Issues - Post-charging 45210.28 ESD Power Clamp Design 45310.29 ESD Power Clamp Design Synthesis - Forward Bias Triggered ESD Power Clamps 45610.30 Series Stacked RC-triggered ESD Power Clamps 45910.31 Triple Well Diode String ESD Power Clamp 46310.32 Bipolar ESD Power Clamps 46410.33 ESD Power Clamp Design Synthesis - Bipolar ESD Power Clamps 46910.34 Bipolar ESD Power Clamps with Frequency Trigger Elements: Capacitance-triggered 48010.35 Silicon Controlled Rectifier Power Clamps 481References 48611 ESD Architecture and Floor Planning 49111.1 ESD Design Floor Plan 49111.2 Peripheral I/O Design 49211.3 Pad Limited Peripheral I/O Design Architecture 49311.4 Pad Limited Peripheral I/O Design Architecture - Staggered I/O 49311.5 Core Limited Peripheral I/O Design Architecture 49511.6 Lumped ESD Power Clamp in Peripheral I/O Design Architecture 49611.7 Lumped ESD Power Clamp in Peripheral I/O Design Architecture in the Semiconductor Chip Corners 49611.8 Lumped ESD Power Clamp in Peripheral I/O Design Architecture - Power Pads 49711.9 Lumped ESD Power Clamp in Peripheral I/O Design Architecture - Master/Slave ESD Power Clamp System 49811.10 Array I/O 49811.11 Array I/O Nibble Architecture 50111.12 Array I/O Pair Architecture 50311.13 Array I/O - Fully Distributed 50411.14 ESD Architecture - Dummy Bus Architecture 50711.15 ESD Architecture - Dummy VDD Bus 50711.16 ESD Architecture - Dummy Ground (VSS) Bus 50811.17 Native Voltage Power Supply Architecture 50811.18 Single Power Supply Architecture 50911.19 Mixed Voltage Architecture 50911.20 Mixed Voltage Architecture - Single Power Supply 50911.21 Mixed Voltage Architecture - Dual Power Supply 51111.22 Mixed Signal Architecture 51411.23 Digital and Analog Floor Plan - Placement of Analog Circuits 51511.24 Mixed Signal Architecture - Digital, Analog, and RF Architecture 51811.25 ESD Power Grid Design 51911.26 I/O to Core Guard Rings 52511.27 Within I/O Guard Rings 52711.28 ESD-to-I/O Off-Chip Driver (OCD) Guard Ring 52711.29 Guard Rings and Computer Aided Design (CAD) Methods 53911.30 Summary and Closing Comments 541References 54112 ESD Digital Design 55112.1 Fundamental Concepts of ESD Design 55112.2 Concepts of ESD Digital Design 55112.3 Device Response to External Events 55212.4 Alternative Current Loops 55312.5 Decoupling of Feedback Loops 55412.6 Decoupling of Power Rails 55412.7 Local and Global Distribution 55412.8 Usage of Parasitic Elements 55512.9 Unused Section of a Semiconductor Device, Circuit, or Chip Function 55612.10 Unused Corners 55612.11 Unused White Space 55612.12 Impedance Matching Between Floating and Non-floating Networks 55612.13 Unconnected Structures 55712.14 Symmetry 55712.15 Design Synthesis 55712.16 ESD, Latchup, and Noise 55912.17 Structures Under Bond Pads 57412.18 Summary and Closing Comments 575References 57613 ESD Analog Design 58313.1 Analog Design: Local Matching 58313.2 Analog Design: Global Matching 58313.3 Symmetry 58413.4 Analog Design - Local Matching 58413.5 Analog Design - Global Matching 58413.6 Common Centroid Design 58613.7 Common Centroid Arrays 58613.8 Interdigitation Design 58613.9 Common Centroid and Interdigitation Design 58713.10 Dummy Resistor Layout 59313.11 Thermoelectric Cancelation Layout 59313.12 Electrostatic Shield 59313.13 Interdigitated Resistors and ESD Parasitics 59413.14 Capacitor Element Design 59513.15 Inductor Element Design 59613.16 ESD Failure in Inductors 59713.17 Inductor Physical Variables 59813.18 Inductor Element Design 59913.19 Diode Design 59913.20 Analog ESD Circuits 60213.21 ESD MOSFETs 60713.24 Analog Differential Pair Common Centroid Design Layout - Signal-pin to Signal-pin and Parasitic ESD Elements 62013.25 Summary and Closing Comments 624References 62414 ESD RF Design 62914.1 Fundamental Concepts of ESD Design 62914.2 Fundamental Concepts of RF ESD Design 63214.3 RF CMOS Input Circuits 63714.4 RF CMOS Impedance Isolation LC Resonator ESD Networks 64714.5 RF CMOS LC-diode Networks Experimental Results 64814.6 RF CMOS LNA ESD Design - Low Resistance ESD Inductor and ESD Diode Clamping Elements in Pi-configuration 65014.7 RF CMOS T-coil Inductor ESD Input Network 65314.8 RF CMOS Distributed ESD Networks 65514.9 RF CMOS Distributed ESD-RF Networks 65614.10 RF CMOS Distributed RF-ESD Networks Using Series Inductors and Dual-diode Shunts 65614.11 RF CMOS Distributed RF-ESD Networks Using Series Inductors and MOSFET Parallel Shunts 65914.12 RF CMOS Distributed ESD Networks - Transmission Lines and Co-planar Waveguides 66114.13 RF CMOS - ESD and RF LDMOS Power Technology 66314.14 Summary and Closing Comments 666References 66615 ESD Power Electronics Design 68115.1 Reliability Technology Scaling and the Reliability Bathtub Curve 68115.2 Input Circuitry 68615.3 Summary and Closing Comments 702References 70216 ESD in Advanced CMOS 70916.1 Interconnects and ESD 70916.2 Aluminum Interconnects 71016.3 Interconnects - Vias 71416.4 Interconnects - Wiring 71516.5 Junctions 71916.6 Titanium Silicide 72516.7 Shallow Trench Isolation 73116.8 LOCOS-bound ESD Structures 73416.9 LOCOS-bound p+/n-well Junction Diodes 73416.10 LOCOS-bound n+ Junction Diodes 73616.11 LOCOS-bound n-well/Substrate Diodes 73716.12 LOCOS-bound Lateral N-Well to N-Well Bipolar ESD Element 73816.13 LOCOS-bound Lateral N+ to N-well Bipolar ESD Element 73816.14 LOCOS-bound Lateral pnp Bipolar ESD Element 73916.15 LOCOS-bound Thick Oxide MOSFET ESD Element 73916.16 Shallow Trench Isolation 73916.17 STI-bound ESD Structures 74116.18 Substrate Modeling - Electrical and Thermal Discretization 74616.19 Heavily Doped Substrates 75016.20 Retrograde Wells and ESD Scaling 76616.21 Triple Well and Isolated MOSFET CMOS 77516.22 Summary and Closing Comments 779References 77917 ESD in Silicon on Insulator 78317.1 Silicon on Insulator (SOI) Technologies 78317.2 Elimination of CMOS Latchup 78417.3 Lack of Vertical Bipolar Transistors 78517.4 Floating Gate Tie Downs 78517.5 Physical Separation of MOSFETs from the Bulk Substrate 78517.6 SOI ESD Design Fundamental Concepts 78617.7 SOI Lateral Diode Structure 79117.8 Transistors - Bulk versus SOI Technology 79117.9 SOI Buried Resistors (BR) Elements 79617.10 Dynamic Threshold MOS (DTMOS) SOI MOSFET 79717.11 SOI P+ Body Contact Abutting n+ Drain 79817.12 Transmission Line Pulse (TLP) Testing of SOI Diode Designs 79817.13 SOI ESD with MOSFET Drain and Body Width Ratio Variation 79917.14 SOI Dual-Gate MOSFET Structure 79917.15 SOI ESD Design - Mixed Voltage T-Shape Layout Style 80017.16 SOI ESD Design: Double Diode Network 80217.17 Bulk to SOI ESD Design Remapping 80317.18 SOI ESD Diode Design Parameters 80417.19 SOI ESD Design in Mixed Voltage Interface Environments 80817.20 Comparison of Bulk with SOI ESD Results 80917.21 SOI ESD Design with Aluminum Interconnects 81017.22 SOI ESD Design with Copper Interconnects 81217.23 SOI ESD Design with Gate Circuitry 81317.24 Summary and Closing Comments 815References 81518 ESD in Analog Circuits 82118.1 Analog Design Circuits 82118.2 Single-ended Receivers 82218.3 Schmitt Trigger Receivers 82218.4 Differential Receivers 82218.5 Comparators 82418.6 Current Sources 82518.7 Current Mirrors 82518.8 Widlar Current Mirror 82618.9 Wilson Current Mirror 82618.10 Voltage Regulators 82718.11 Buck Converters 82818.12 Boost Converters 82818.13 Buck-Boost Converters 82918.14 Cuk Converters 83018.15 Voltage Reference Circuits 83018.16 Brokaw Bandgap Voltage Reference 83018.17 Converters 83118.18 Analog-to-Digital Converter (ADC) 83118.19 Digital-to-Analog Converters (DAC) 83218.20 Oscillators 83218.21 Phase Lock Loop (PLL) Circuits 83218.22 Delay Locked Loop (DLL) 83318.23 Analog and ESD Design Synthesis 83318.24 Analog Chip Architecture - Separation of Analog Power from Digital Power, AVDD-DVDD 83618.25 ESD Failure in Phase Lock Loop (PLL) and System Clock 83718.26 ESD Failure in Current Mirrors 83718.27 ESD Failure in Schmitt Trigger Receivers 83818.28 ESD Design Practice - Prevent ESD Failure in Schmitt Trigger 84018.29 Analog-Digital Architecture: Isolated Digital and Analog Domains 84118.30 ESD Protection Solution - Connectivity of AVDD-to-VDD 84218.31 ESD Solution: Connectivity of AVSS-to-DVSS 84318.32 Digital and Analog Domain with ESD Power Clamps 84318.33 Digital and Analog Domain with Master-Slave ESD Power Clamps 84618.34 High Voltage, Digital, and Analog Domain Floorplan 84618.35 Floor-planning of Digital and Analog 84618.36 Inter-domain Signal Lines ESD Failures 84918.37 Digital-to-Analog Signal Line ESD Failures 84918.38 Digital-to-Analog Core Spatial Isolation 85118.39 Digital-to-Analog Core Ground Coupling 85118.40 Digital-to-Analog Core Resistive Ground Coupling 85218.41 Digital-to-Analog Core Diode Ground Coupling 85218.42 Domain-to-Domain Signal Line ESD Networks 85218.43 Domain-to-Domain Third-party Coupling Networks 85318.44 Domain-to-Domain Cross-domain ESD Power Clamp 85418.45 Digital-to-Analog Domain Moat 85518.46 Analog and ESD Circuit Integration 85518.47 Integrated Body Ties 85618.48 Self-Protecting vs Non-self Protecting Designs 856References 85619 ESD in RF CMOS 86519.1 CMOS and ESD 86519.2 RF CMOS 86519.3 RF CMOS and ESD 86519.4 RF CMOS ESD Failure Mechanisms 86519.5 RF CMOS - ESD Device Comparisons 86619.6 RF ESD Metrics 86719.7 Grounded Gate n-channel MOSFET versus STI Diode 86819.8 Silicon-controlled Rectifier 86919.9 SCR versus GGNMOS 86919.10 Shallow Trench Isolation and Polysilicon Gated Diodes 86919.11 RF ESD Design 87019.12 RF ESD Design Layout - Circular RF ESD Devices 87019.13 Disadvantage of RF ESD Circular Element 87119.14 RF ESD Design - ESD Wiring Design 87219.15 RF ESD Design - Loading Capacitance 87219.16 Metal Capacitance 87319.17 Analog Metal (AM) 87319.18 RF ESD Design Practices 87419.19 RF Passives - ESD and Schottky Barrier Diodes 87419.20 Schottky Barrier Diodes and Metallurgy 87519.21 Silicon Germanium Schottky Barrier Diodes 87619.22 Schottky Barrier RF ESD Design Practice 87719.23 RF Passives - ESD and Inductors 87719.24 Quality Factor, Q 87819.25 Incremental Model of an Inductor 87819.26 Inductor Coil Parameters 87819.27 RF Passives - ESD and Capacitors 88219.28 Capacitors and RF Applications 88219.29 Capacitors in ESD Networks 88219.30 Types of Radio Frequency Capacitors 88319.31 Metal-Oxide-Semiconductor and Metal-Insulator-Metal Capacitors 88319.32 Varactors and Hyper-abrupt Junction Varactor Capacitors 88419.33 Metal-ILD-Metal Capacitors 88419.34 Vertical Parallel Plate (VPP) Capacitors 88419.35 Tips: ESD RF Design Practices for Capacitors 88519.36 Summary and Closing Comments 886Problems 886References 88820 ESD in Silicon Germanium 89120.1 Heterojunctions Bipolar Transistors 89120.2 Silicon Germanium 89120.3 Silicon Germanium HBT Devices 89220.4 Silicon Germanium Device Structure 89320.5 Silicon Germanium Film Deposition 89420.6 Silicon Germanium Emitter-Base Region 89520.7 Silicon Germanium Physics 89520.8 Silicon Germanium Bandgap 89620.9 Silicon Germanium Intrinsic Temperature 89620.10 Position-dependent Silicon Germanium Profile 89620.11 Position-dependent Intrinsic Temperature 89720.12 SiGe Collector Current with Graded Germanium Concentration 89720.13 Silicon Germanium ESD and Time Constants 89820.14 Silicon Germanium Base Transit Time 89820.15 Silicon Germanium Breakdown Voltages 89820.16 Silicon Germanium ESD Measurements 89920.17 Silicon Germanium Collector-to-Emitter ESD Stress 89920.18 Transmission Line Pulse Testing of Silicon Germanium HBT 89920.19 Transmission Line Pulse (TLP) I-V Characteristic 89920.20 Wunsch-Bell Characteristic of Silicon Germanium HBT 90120.21 Comparison of Silicon Germanium HBT and Silicon BJT 90120.22 Wunsch-Bell Characteristic of SiGe HBT versus Si BJT 90220.23 Intrinsic Base Resistance in SiGe HBT 90420.24 SiGe HBT Electro-thermal HBM Simulation of Collector-Emitter Stress 90420.25 Silicon Germanium Transistor Emitter-Base Design 90520.26 Epitaxial-Base Hetero-Junction Bipolar Transistor (HBT) Emitter-Base Design 90720.27 Self-aligned Silicon Germanium HBT Device 90720.28 Non-Self Aligned Silicon Germanium HBT 90820.29 Emitter-Base Design RF Frequency Performance Metrics 90820.30 SiGe HBT Emitter-Base Resistance Model 90920.31 SiGe HBT Emitter-Base Design and Silicide Placement 90920.32 Silicide Material and ESD 91020.33 Titanium Silicide and ESD 91120.34 Cobalt Salicide 91320.35 Self-aligned (SA) Emitter Base Design 91420.36 Non-Self Aligned (NSA) Emitter Base Design 91720.37 Non-Self Aligned HBT Human Body Model (HBM) Step Stress 91820.38 Transmission Line Pulse (TLP) Step Stress 91820.39 RF Testing of SiGe HBT Emitter-Base Configuration 92120.40 Unity Current Gain Cutoff Frequency - Collector Current Plots 92320.41 f MAX and f T 92420.42 Electrothermal Simulation of Emitter-Base Stress 92520.43 Field-Oxide (FOX) Isolation Defined Silicon Germanium Heterojunction Bipolar Transistor HBM Data 92620.44 Silicon Germanium HBT Multiple-emitter Study 92720.45 RF ESD Design Practice 92720.46 Silicon Germanium ESD Failure Mechanisms 92820.47 Summary and Closing Comments 928References 92821 ESD in Silicon Germanium Carbon 93521.1 Heterojunctions and Silicon Germanium Carbon Technology 93521.2 Silicon Germanium Carbon 93521.3 Silicon Germanium Carbon Collector-Emitter ESD Measurements 93721.4 Silicon Germanium Transistor Emitter-Base Design 94021.5 Silicon Germanium Carbon - ESD-Induced S-Parameter Degradation 94321.6 Silicon Germanium Carbon ESD Failure Mechanisms 94521.7 Summary and Closing Comments 945References 94622 ESD in GaAs 95122.1 Gallium Arsenide Technology and ESD 95122.2 Gallium Arsenide Energy-to-Failure, and Power-to-Failure 95122.3 Gallium Arsenide ESD Failures in Active and Passive Elements 95422.4 Gallium Arsenide HBT Devices and ESD 95522.5 Gallium Arsenide HBT Device ESD Results 95622.6 Gallium Arsenide HBT Diode Strings 95722.7 Gallium Arsenide HBT-based Passive Elements 95922.8 GaAs HBT Base-Collector Varactor 95922.9 Gallium Arsenide Technology Table of Failure Mechanisms 96022.10 Application - GaAs Power Amplifier in a Cell Phone 96122.11 Summary and Closing Comments 965Questions 965References 96623 ESD in Bulk and SOI FINFET 97123.1 Early FinFET Structures 97123.2 FinFET Structure and Design Parameters 97123.3 FinFET Parameters 97323.4 Summary and Closing Comments 977References 97724 MEMs 97924.1 Micro-electromechanical (MEM) Devices 97924.2 ESD Concerns in Micro-electromechanical (MEM) Devices 98024.3 Actuators 98224.5 Micro-electromechanical (MEM) Mirrors 98524.6 Summary and Closing Comments 989References 98925 Magnetic Recording 99125.1 Magnetic Recording Technology 99125.2 Summary and Closing Comments 995References 99526 Photomasks 100326.1 Photomasks and Reticles 100326.2 ESD Concerns in Photomasks 100326.3 Avalanche Breakdown in Photomasks 100426.4 Electrical Model in Photomasks 100726.5 Failure Defects in Photomasks 100826.6 Summary and Closing Comments 1011References 1011Appendix Table of Acronyms 1013A Glossary of Terms - EMC Terminology 1015B Appendix B. ESD Standards 1017B.1 ESD Association 1017B.2 International Organization of Standards 1018B.3 Department of Defense 1018B.4 Military Standards 1019B.5 Airborne Standards and Lightning 1019C Index 1021D Wiley Series in Electrostatic Discharge (ESD) and Electrical Overstress (EOS) 1055D.1 Additional Wiley Texts 1055E ESD Design Rules 1057E.1 ESD Design Rule Check (DRC) 1057E.2 Electrostatic Discharge (ESD) Layout Versus Schematic (LVS) Verification 1058E.3 ESD Electrical Rule Check (ERC) 1059F Guard Ring Design Rules 1061F.1 Latchup Design Rule Checking (DRC) and Guard Rings 1061F.2 Latchup Electrical Rule Check (ERC) 1063F.3 Guard Ring Resistance 1064G EOS Design Rules and Checklist 1067G.1 Electrical Overstress (EOS) Design Rule Checking 1067G.2 Electrical Overstress (EOS) Layout Versus Schematic (LVS) Verification 1067G.3 Electrical Overstress (EOS) Electrical Rule Check (ERC) 1068H Latchup Design Rules 1069H.1 Latchup Design Rule Checking (DRC) 1069H.2 Latchup Electrical Rule Check (ERC) 1072I ESD Cookbook 1077I.1 Electrostatic Discharge (ESD) Cookbook 1077J EOS Cookbook 1079J.1 Electrical Overstress (EOS) Cookbook 1079K Latchup Cookbook 1081K.1 Latchup Design Rule Checking (DRC) 1081K.2 Latchup Electrical Rule Check (ERC) 1083L ESD Design and Release Check List 1087L.1 ESD Design Release 1087L.2 Electrostatic Discharge (ESD) Checklists 1087M EOS Design and Release Checklist 1089M.1 Electrical Overstress (EOS) and ESD Design Release 1089M.2 Electrical Overstress (EOS) Design Release Process 1089M.3 Electrical Overstress (EOS) Checklists 1090M.4 An EOS Checklist 1091N Latchup Design and Release Checklist 1093N.1 Latchup Design Rule Checking (DRC) 1093N.2 Latchup Electrical Rule Checking (ERC) 1095N.3 Latchup Checklists 1095N.4 A Latchup Design and Release Checklist 1096Index 1097

O autorze

Steven H. Voldman is the first IEEE Fellow for contributions in ESD protection in CMOS, SOI, and Silicon Germanium technology. He has been at the forefront of every major development in semiconductor technology over the past thirty years.