Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits

ISBN-13: 9781138075771 / Angielski / Miękka / 2017 / 259 str.

Opis

Advances in design methods and process technologies have resulted in a continuous increase in the complexity of integrated circuits (ICs). However, the increased complexity and nanometer-size features of modern ICs make them susceptible to manufacturing defects, as well as performance and quality issues. Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits covers common problems in areas such as process variations, power supply noise, crosstalk, resistive opens/bridges, and design-for-manufacturing (DfM)-related rule violations. The book also addresses testing for small-delay defects (SDDs), which can cause immediate timing failures on both critical and non-critical paths in the circuit. 　

• Overviews semiconductor industry test challenges and the need for SDD testing, including basic concepts and introductory material
• Describes algorithmic solutions incorporated in commercial tools from Mentor Graphics
• Reviews SDD testing based on "alternative methods" that explores new metrics, top-off ATPG, and circuit topology-based solutions
• Highlights the advantages and disadvantages of a diverse set of metrics, and identifies scope for improvement

Written from the triple viewpoint of university researchers, EDA tool developers, and chip designers and tool users, this book is the first of its kind to address all aspects of SDD testing from such a diverse perspective. The book is designed as a one-stop reference for current industrial practices, research challenges in the domain of SDD testing, and recent developments in SDD solutions.

Spis treści

Fundamentals of Small-Delay Defect Testing. Timing-Aware ATPG: K Longest Paths. Timing-Aware ATPG. Faster-than-At-Speed: Faster-than-at-Speed Test for Screening Small-Delay Defects. Circuit Path Grading Considering Layout, Process Variations, and Cross Talk. Alternative Methods: Output Deviations-Based SDD Testing. Hybrid/Top-off Test Pattern Generation Schemes for Small-Delay Defects. Circuit Topology-Based Test Pattern Generation for Small-Delay Defects. SDD Metrics: Small-Delay Defect Coverage Metrics. Conclusion. References.