System-On-A-Chip Verification: Methodology and Techniques

ISBN-13: 9781475774689 / Angielski / Miękka / 2013 / 372 str.

Prakash Rashinkar; Peter Paterson;Leena Singh

Opis

This is the first book to cover verification strategies and methodologies for SOC verification from system level verification to the design sign-off. All the verification aspects in this exciting new book are illustrated with a single reference design for Bluetooth application.

Spis treści

Authors. Acknowledgements. Foreword. 1: Introduction. 1.1. Technology Challenges. 1.2. Verification Technology Options. 1.3. Verification Methodology. 1.4. Testbench Creation. 1.5. Testbench Migration. 1.6. Verification Languages. 1.7. Verification IP Reuse. 1.8. Verification Approaches. 1.9. Verification and Device Test. 1.10. Verification Plans. 1.11. Bluetooth SOC: A Reference Design. 2: System-Level Verification. 2.1. System Design. 2.2. System Verification. 2.3. Bluetooth SOC. 3: Block-Level Verification. 1.1. IP Blocks. 3.2. Block Level Verification. 3.3. Block Details of the Bluetooth SOC. 3.4. Lint Checking. 3.5. Formal Model Checking. 3.6. Functional Verification/Simulation. 3.7. Protocol Checking. 3.8. Directed Random Testing. 3.9. Code Coverage Analysis. 4: Analog/Mixed Signal Simulation. 4.1. Mixed-Signal Simulation. 4.2. Design Abstraction Levels. 4.3. Simulation Environment. 4.4. Using SPICE. 4.5. Simulation Methodology. 4.6. Bluetooth SOC Digital-to-Analog Converter. 4.7. Chip-Level Verification with an AMS Block. 5: Simulation. 5.1. Functional Simulation. 5.2. Testbench Wrappers. 5.3. Event-Based Simulation. 5.4. Cycle-Based Simulation. 5.5. Simulating the ASB/APB Bridge. 5.6. Mixed-Event/Cycle-Based Simulation. 5.7. Transaction-Based Verification. 5.8. Simulation Acceleration. 6: Hardware/Software Co-verification. 6.1. HW/SW Co-verification Environment. 6.2. Emulation. 6.3. Soft or Virtual Prototypes. 6.4. Co-verification. 6.5. Rapid Prototype Systems. 6.6. Comparing HW/SW Verification Methods. 6.7. FPGA-Based Design. 6.8. Developing Printed Circuit Boards. 6.9.Software Testing. 7: Static Netlist Verification. 7.1. Netlist Verification. 7.2.Bluetooth SOC Arbiter. 7.3. Equivalence Checking. 7.4. Static Timing Verification. 8: Physical Verification and Design Sign-off. 8.1. Design Checks. 8.2. Physical Effects Analysis. 8.3. Design Sign-off. Glossary. Index.