Substrate Noise Coupling in Rfics

ISBN-13: 9781402081651 / Angielski / Twarda / 2008 / 119 str.

Ahmed Helmy; Mohammed Ismail

Opis

The book reports modeling and simulation techniques for substrate noise coupling effects in RFICs and introduces isolation structures and design guides to mitigate such effects with the ultimate goal of enhancing the yield of RF and mixed signal SoCs. The book further reports silicon measurements, and new test and noise isolation structures. To the authors' knowledge, this is the first title devoted to the topic of substrate noise coupling in RFICs as part of a large SoC.

Spis treści

Abstract. Dedication. Acknowledgements. Vita. List of Tables. List of Figures. Chapter 1. Introduction. Motivation and Research Objectives. Contributions Thesis Organization. Chapter 2. Analysis of Substrate Noise Coupling. Process Regions. Process cross sections. Connection of devices to the substrate. Devices directly connected to the substrate network. Devices indirectly connected to the substrate network. Noise coupling mechanism. Substrate Noise Injection Mechanisms. Substrate Noise Reception Mechanisms. Substrate Noise Transmission Mechanisms. Substrate doping profile tradeoffs. Substrate Model extraction in the IC design flow. Doping Profile Considerations. Substrate model extraction kernels. Finite Difference method. Boundary Element method. Comparison between the two Techniques. Approximations in the Model Extraction Algorithm. Conclusion. Chapter 3. Experimental Data to calibrate the design flow. Introduction. The test chip. Baseline Isolation. Data analysis. Effect of p-guard ring on isolation. Data analysis. Effect of n-guard ring on isolation. Data analysis. Effect of deep n-well on isolation. Data analysis. Effect of deep trench on isolation. Data analysis. De-embedding. Conclusion. Chapter 4. Design Guide for Substrate Noise Isolation for RF Applications Introduction. Isolation in Low resistivity substrate. Isolation vs. Frequency for different isolation structures. Effect of back plane connection on the noise isolation in high resistivity substrates. Substrate Contacts: Front side or Backside? Both. P+ Guard Ring Isolation. Guard Ring Isolation vs. D. Guard Ring grounding scheme. Guard Ring Isolation vs. d. Guard Ring Isolation vs. 'w'. P+ and N+ Guard Rings Isolation. Floor planning techniques to minimize coupling. Circuit techniques to minimize coupling. Active guard rings. Conclusion. Chapter 5. On Chip Inductor Design Flow. Introduction. Integrated Inductors. Inductor Design Flow. Analytical exploration of the design space. Inductor Model and Substrate Parasitics. Calibrating the field solver. Model fit. DFM effects. Impact of bumps. Impact of temperature variation. Impact of process variation. Impact of metal fill. Conclusion. Chapter 6. Case studies for the impact and remedy of substrate noise coupling. Introduction. System Level Case study. Background. Design Data. Block Level Case study. Design details. Device Level Case study. Conclusion. Chapter 7. Conclusion and Future work. Appendix A Scattering Parameters. Appendix B Measurements Setup. Bibliography.

O autorze

Mohammed Ismail is the Springer Series Advisor for the Analog Circuits and Signal Processing book series

Blurb

Substrate Noise Coupling in RFICs addresses substrate noise coupling in RF and mixed signal ICs when used in a system on chip (SoC) containing digital ICs as well. This trend of integrating RF, mixed signal ICs with large digital ICs is found in many of today's commercial ICs such as single chip Wi-Fi or Bluetooth solutions and is expected to grow rapidly in the future. The book reports modeling and simulation techniques for substrate noise coupling effects in RFICs and introduces isolation structures and design guides to mitigate such effects with the ultimate goal of enhancing the yield of RF and mixed signal SoCs . This is particularly critical when process feature sizes scale down to the nano meter range.

Substrate Noise Coupling in RFICs reports silicon measurements, new test and noise isolation structures as well as calibration of a design flow used in the design and debug phases of RFICs. A design guide is articulated to be used by RFIC designers to maximize signal isolation and optimize chip floor plan, power and ground domains. Industrial examples of RFICs are given as demonstration vehicles to validate the proposed techniques. Some emphasis is put on the design of on-chip spiral inductors and the impact of the substrate on their performance. To our knowledge, this is the first title devoted to the topic of substrate noise coupling in RFICs as part of a large SoC.