Single Port Memory Design Using VHDL » książka
Single Port Memory Design Using VHDL
ISBN-13: 9783846590607 / Angielski / Miękka / 2014 / 100 str.
In today's fast paced technology race there are many aspects of a computer that can be improved upon. Memory is an integral part of how a computer works and involves many different complex levels of hierarchy. Semiconductor memory is an electronic data storage device often used as computer memory, implemented on semiconductor-basis integrated circuits. It is made in many different types and technologies. A simple yet efficient method is presented to explore the design space for memory synthesis which deals with single-port memory synthesis according to the design constraints. The application of this method to different synthesis examples is illustrated and demonstrated. With suitable modifications, the technique could be applied to multiport memory synthesis in which the maximum number of read ports is different from the maximum number of write ports. Memory is designed in VHDL to produce the RTL schematic of the desired circuit. After that, the generated schematic can be verified using simulation software which shows the waveforms of inputs and outputs of the circuit after generating the appropriate testbench. All the chapters start with a brief explanation of design stage.
In todays fast paced technology race there are many aspects of a computer that can be improved upon. Memory is an integral part of how a computer works and involves many different complex levels of hierarchy. Semiconductor memory is an electronic data storage device often used as computer memory, implemented on semiconductor-basis integrated circuits. It is made in many different types and technologies. A simple yet efficient method is presented to explore the design space for memory synthesis which deals with single-port memory synthesis according to the design constraints. The application of this method to different synthesis examples is illustrated and demonstrated. With suitable modifications, the technique could be applied to multiport memory synthesis in which the maximum number of read ports is different from the maximum number of write ports. Memory is designed in VHDL to produce the RTL schematic of the desired circuit. After that, the generated schematic can be verified using simulation software which shows the waveforms of inputs and outputs of the circuit after generating the appropriate testbench. All the chapters start with a brief explanation of design stage.
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