Self Aware Security for Real Time Task Schedules in Reconfigurable Hardware Platforms

ISBN-13: 9783030797034 / Angielski / Miękka / 2022

Krishnendu Guha;Sangeet Saha;Amlan Chakrabarti

Opis

This book focuses on how real-time task schedules for reconfigurable hardware-based embedded platforms may be affected due to the vulnerability of hardware and proposes self-aware security strategies to counteract the various threats. The emergence of Industry 4.0 has witnessed the deployment of reconfigurable hardware or field programmable gate arrays (FPGAs) in diverse embedded applications. These are associated with the execution of several real-time tasks arranged in schedules. However, they are associated with several issues. Development of fully and partially reconfigurable task schedules are discussed that eradicates the existing problems. However, such real-time task schedules may be jeopardized due to hardware threats. Analysis of such threats is discussed and self-aware security techniques are proposed that can detect and mitigate such threats at runtime.

Spis treści

Chapter 1: Introduction

(a)   Reconfigurable hardware based embedded systems

(b)   Importance of Real Time Scheduling for such embedded architectures

(c)   Importance of Self Aware Security for such architectures

Chapter 2: Background

(a) Scheduling for embedded real time tasks and limitations of existing techniques

(b) Security related to hardware attacks and limitations of existing techniques

Chapter 3:  A novel real-time scheduling for FPGAs having slotted area model

This chapter presents deadline-partition oriented scheduling methodologiesfor periodic hard real-time dynamic task sets on fully and partiallyreconfigurable FPGAs in which the floor of the FPGA is assumed to be statically equi-partitioned into a set of homogeneous tiles such that anyarbitrary task of the given task set may be feasibly mapped into the areaof a given tile.

Chapter 4: A novel real-time scheduling for FPGAs having flexible area model

This chapter presents scheduling methodologies for periodic dependent hard real-time dynamic task sets on fully and partially reconfigurable FPGAs in which the floor of the FPGA follows flexible area model such that any task can be placed anywhere within the floor area. This will work will attempt to solve both the temporal and spatial aspects of the scheduling.

Chapter 5: Denial of Service Attacks for Real Time Scheduling and Related Mitigation Techniques

This chapter presents threat analysis associated with denial of service attacks due to delay inducing hardware trojans in embedded architectures for the scheduling strategies presenteed in Chapter 3 and 4. A self aware security module is also presented that detects and mitigates the threat.

Chapter 6: Erroneous Result Generation Attack for Real Time Scheduling and Related Mitigation Technique

This chapter presents threat analysis associated with generation of erroneous results that may jeopardize the real time task schedules presented in Chapter 3 and 4. Related detection and mitigation techniques are presented alongwith. In addition to this, it is also described how related modifications of the self aware security module can ensure security for the present scenario.

Chapter 7: Conclusion

In this book, we present the importance of real time scheduling for reconfigurable hardware based embedded platforms and related security needs. We present limitations of existing techniques and present some new real time scheduling techniques suitable for the embedded platform. We also focus on how denial of service and erroneous result generation may take place on the real time schedules due to vulnerability of hardware. Related detection and mitigation techniques are discussed, along with description of a self aware module that facilitates detection and mitigation from such threats.

O autorze

Dr. Krishnendu Guha is presently an Assistant Professor (On Contract) at National Institute of Technology (NIT), Jamshedpur, India. Prior to this, he was a Visiting Scientist in Indian Statistical Institute (ISI), Kolkata, India from December 2020-February 2021. He was also an Intel India Research Fellow from December 2019- December 2020. He has completed his Ph.D. from University of Calcutta. In his Ph.D. tenure, he received the prestigious INSPIRE Fellowship Award from the Department of Science and Technology, Government of India and the Intel India Final Year Ph.D. Fellowship Award from Intel Corporations, India. He completed his MTech from University of Calcutta, where he was the recipient of the University Gold Medal for securing the First Class First Rank. His present research arena encompasses embedded security, with a flavor of artificial intelligence and nature-inspired strategies.

Dr. Sangeet Saha received his Ph.D. degree in Information Technology from the University of Calcutta, India in 2018. He received the TCS Industry Fellowship Award during his Ph.D. After submitting his Ph.D. thesis in 2017, he worked as a visiting scientist at Indian Statistical Institute (ISI) Kolkata, India. Since May 1, 2018 he is a Senior Research Officer in EPSRC National Centre for Nuclear Robotics, based in the EIS Lab, School of Computer Science and Electronic Engineering at University of Essex, UK. Primarily, his research expertise is in embedded systems, with specific interests that include real-time scheduling, scheduling for reconfigurable computers, fault-tolerance, and approximation-based real-time computing.

Prof. (Dr.) Amlan Chakrabarti is presently Professor and Director of A. K. Choudhury School of Information Technology (AKCSIT), University of Calcutta. Prior to this, he completed his post-doctoral research at Princeton University after completing his Ph.D. from the University of Calcutta in association with ISI, Kolkata. He has been associated with research projects funded by government agencies and industries related to Reconfigurable Architecture, VLSI Design, Security for Cyber-physical Systems, Internet of Things, Machine Learning, Computer Vision and Quantum Computing. He is the Series Editor of Springer Transactions on Computer Systems and Networks and Associate Editor of Elsevier Journal of Computers and Electrical Engineering. His present research interests include Reconfigurable Computing, Embedded Systems Design, VLSI Design, Quantum Computing and Computer Vision. He is a Distinguished Visitor of IEEE Computer Society and Distinguished Speaker of ACM (2017-2020).