Reliability of RoHS-Compliant 2D and 3D IC Interconnects

ISBN-13: 9780071753791 / Angielski / Twarda / 2010 / 640 str.

John Lau

Opis

Proven 2D and 3D IC lead-free interconnect reliability techniques Reliability of RoHS-Compliant 2D and 3D IC Interconnects offers tested solutions to reliability problems in lead-free interconnects for PCB assembly, conventional IC packaging, 3D IC packaging, and 3D IC integration. This authoritative guide presents the latest cutting-edge reliability methods and data for electronic manufacturing services (EMS) on second-level interconnects, packaging assembly on first-level interconnects, and 3D IC integration on microbumps and through-silicon-via (TSV) interposers. Design reliable 2D and 3D IC interconnects in RoHS-compliant projects using the detailed information in this practical resource. Covers reliability of:

• 2D and 3D IC lead-free interconnects
• CCGA, PBGA, WLP, PQFP, flip-chip, lead-free SAC solder joints
• Lead-free (SACX) solder joints
• Low-temperature lead-free (SnBiAg) solder joints
• Solder joints with voids, high strain rate, and high ramp rate
• VCSEL and LED lead-free interconnects
• 3D LED and 3D MEMS with TSVs
• Chip-to-wafer (C2W) bonding and lead-free interconnects
• Wafer-to-wafer (W2W) bonding and lead-free interconnects
• 3D IC chip stacking with low-temperature bonding
• TSV interposers and lead-free interconnects
• Electromigration of lead-free microbumps for 3D IC integration

Spis treści

Ch 1. Introduction to RoHS Compliant Semiconductor and Packaging Technologies; Ch 2. Reliability Engineering of Lead-Free Interconnects; Ch 3. Notes on Failure Criterion; Ch 4. Reliability of 1657-Pin CCGA Lead-Free Solder Joints; Ch 5. Reliability of PBGA Lead-Free Solder Joints (With and Without Underfills); Ch 6. Reliability of LED Lead-Free Interconnects; Ch 7. Reliability of VCSEL Lead-Free Interconnects; Ch 8. Reliability of Low-Temperature Lead-Free (SnBiAg) Solder Joints; Ch 9. Reliability of Lead-Free (SACX) Solder Joints; Ch 10. Chip-to-Wafer (C2W) Bonding and Lead-Free Interconnect Reliability; Ch 11. Wafer-to-Wafer (W2W) Bonding and Lead-Free Interconnect Reliability; Ch 12. Through-Silicon-Via (TSV) Interposer Reliability; Ch 13. Electromigration of Lead-Free Microbumps for 3D IC Integration; Ch 14. Effects of Dwell-Time and Ramp-Rate on SAC Thermal Cycling Test Results; Ch 15. Effects of High Strain Rate (Impact) on SAC Solder Balls/Bumps; Ch 16. Effects of Voids on Solder Joints Reliability; Index

O autorze

John H. Lau received his Ph.D. degree in Theoretical and Applied Mechanics from the University of Illinois (1977), a M.A.Sc. degree in Structural Engineering from the University of British Columbia (1973), a second M.S. degree in Engineering Physics from the University of Wisconsin (1974), and a third M.S. degree in Management Science from Fairleigh Dickinson University (1981). He also has a B.E. degree in Civil Engineering from National Taiwan University (1970). John is an interconnection technology scientist at Agilent Technologies, Inc. His current interests cover a broad range of electronic and optoelectronic packaging and manufacturing technology. Prior to Agilent, he worked for Express Packaging Systems, Hewlett-Packard Company, Sandia National Laboratory, Bechtel Power Corporation, and Exxon Production and Research Company. With more than 30 years of R&D and manufacturing experience in the electronics, petroleum, nuclear, and defense industries, he has given over 200 workshops, authored and co-authored over 180 peer reviewed technical publications, and is the author and editor of 13 books: Solder Joint Reliability; Handbook of Tape Automated Bonding; Thermal Stress and Strain in Microelectronics Packaging; The Mechanics of Solder Alloy Interconnects; Handbook of Fine Pitch Surface Mount Technology; Chip On Board Technologies for Multichip Modules; Ball Grid Array Technology; Flip Chip Technologies; Solder Joint Reliability of BGA, CSP, Flip Chip, and Fine Pitch SMT Assemblies; Electronics Packaging: Design, Materials, Process, and Reliability; Chip Scale Package (CSP): Design, Materials, Process, Reliability, and Applications; Low Cost Flip Chip Technologies for DCA, WLCSP, and PBGA Assemblies, and Microvias for Low Cost, High Density Interconnects. John served as one of the associate editors of the IEEE Transactions on Components, Packaging, and Manufacturing Technology and ASME Transactions, Journal of Electronic Packaging. He also served as general chairman, program chairman, and session chairman, and invited speaker of several IEEE, ASME, ASM, MRS, IMAPS, SEMI, and SMI International conferences. He received a few awards from ASME and IEEE for best papers and outstanding technical achievements, and is an ASME Fellow and an IEEE Fellow. He is listed in American Men and Women of Science and Who's Who in America.