Recent Advances in Pmos Negative Bias Temperature Instability: Characterization and Modeling of Device Architecture, Material and Process Impact

ISBN-13: 9789811661198 / Angielski / Twarda / 2021 / 336 str.

Mahapatra, Souvik

Opis

This book covers advances in Negative Bias Temperature Instability (NBTI) and will prove useful to researchers and professionals in the semiconductor devices areas. NBTI continues to remain as an important reliability issue for CMOS transistors and circuits. Development of NBTI resilient technology relies on utilizing suitable stress conditions, artifact free measurements and accurate physics-based models for the reliable determination of degradation at end-of-life, as well as understanding the process, material and device architectural impacts. This book discusses: 

Ultra-fast measurements and modelling of parametric drift due to NBTI in different transistor architectures: planar bulk and FDSOI p-MOSFETs, p-FinFETs and GAA-SNS p-FETs, with Silicon and Silicon Germanium channels. 

BTI Analysis Tool (BAT), a comprehensive physics-based framework, to model the measured time kinetics of parametric drift during and after DC and AC stress, at different stress and recovery biases and temperature, as well as pulse duty cycle and frequency. 

The Reaction Diffusion (RD) model is used for generated interface traps, Transient Trap Occupancy Model (TTOM) for charge occupancy of the generated interface traps and their contribution, Activated Barrier Double Well Thermionic (ABDWT) model for hole trapping in pre-existing bulk gate insulator traps, and Reaction Diffusion Drift (RDD) model for bulk trap generation in the BAT framework; NBTI parametric drift is due to uncorrelated contributions from the trap generation (interface, bulk) and trapping processes. 

Analysis and modelling of Nitrogen incorporation into the gate insulator, Germanium incorporation into the channel, and mechanical stress effects due to changes in the transistor layout or device dimensions; similarities and differences of (100) surface dominated planar and GAA MOSFETs and (110) sidewall dominated FinFETs are analysed.

Spis treści

1. Basic features, process dependence and variability of NBTI in p-MOSFETs

1.1. Introduction

1.2. Measurement of NBTI kinetics

1.2.1. Ultra-fast measure-stress-measure method

1.2.2. Time evolution of stress and recovery

1.2.3. Impact of measurement delay

1.2.4. Voltage and temperature dependence 

1.2.5. Duty cycle and frequency dependence

1.2.6. Empirical estimation of end-of-life degradation

1.3. Overview of NBTI process dependence 

1.3.1. Impact of SiGe channel

1.3.2. Impact of Nitrogen

1.3.3. Impact of gate stack thickness scaling 

1.3.4. Impact of fin dimension scaling

1.3.5. Impact of layout

1.4. NBTI in small area devices

1.4.1. Stress and recovery kinetics

1.4.2. Distribution of degradation

1.4.3. Correlation of variability and variable NBTI

1.4.4. Random Telegraph Noise

1.5. Physical mechanism of NBTI – an overview

1.6. Summary

2. NBTI kinetics modeling framework 

2.1. Introduction

2.2. Overview of NBTI modeling framework

2.3. Generation and passivation of interface traps

2.3.1. Double interface Reaction-Diffusion (RD) model

2.3.2. Physical mechanism of defect depassivation

2.3.3. A discussion on RD model parameters

2.3.4. DCIV measurement method

2.3.5. Prediction of DCIV data

2.3.6. Analysis of Ge% and N% impact

2.3.7. Comparison of continuum and stochastic frameworks

2.4. Occupancy of generated interface traps

2.4.1. Transient Trap Occupancy Model (TTOM)

2.4.2. Validation of TTOM framework

2.5. Hole trapping in pre-existing bulk traps

2.6. Validation of TTOM enabled RD and hole trapping

2.7. Time Dependent Defect Spectroscopy (TDDS) analysis

2.8. Generation of bulk traps

2.9. Validation of TTOM enabled RD and bulk trap generation

2.10. Summary

3. Modeling of NBTI kinetics in HKMG Si and Si-capped SiGe p-MOSFETs

3.1. Introduction 

3.2. Description of process splits

3.3. Analysis of Gate First HKMG planar devices 

3.3.1. DC stress and recovery kinetics

3.3.2. Impact of measurement delay

3.3.3. Nitrogen impact on NBTI parameters

3.3.4. AC stress kinetics

3.4. Analysis of mean stress-recovery kinetics from small area devices

3.5. Process dependence of model parameters

3.6. Estimation of end-of-life degradation 

3.6.1. Calculation by empirical method

3.6.2. Calculation by physical model

3.6.3. Comparison of empirical and physical methods

3.7. Analysis of Si-capped SiGe planar devices

3.7.1. Stress and recovery kinetics

3.7.2. Voltage acceleration factor

3.7.3. Process dependence of model parameters 

3.7.4. Estimation of end-of-life degradation

3.8. Summary

4. Modeling of NBTI kinetics in HKMG Si and SiGe FDSOI MOSFETs

4.1. Introduction 

4.2. Description of process splits 

4.3. Analysis of measured data

4.3.1. Time kinetics of stress and recovery

4.3.2. Impact of Ge% and N%

4.3.3. Impact of layout (STI to active spacing)

4.3.4. Process dependence of model parameters

4.4. Explanation of process dependence

4.4.1. Impact of Ge% and N%

4.4.2. Impact of layout effect 

4.5. Estimation of end-of-life degradation 

4.6. Summary

5. Modeling of NBTI kinetics in RMG HKMG Si FinFETs

5.1. Introduction

5.2. Description of process splits

5.3. Analysis of measured data 

5.3.1. DC stress and recovery kinetics 

5.3.2. Voltage and temperature dependence 

5.3.3. AC stress and recovery kinetics

5.3.4. Duty cycle and frequency dependence 

5.4. Comparison of FinFET architectures

5.4.1. DC stress and recovery kinetics 

5.4.2. Voltage and temperature dependence 

5.4.3. AC stress and recovery kinetics

5.4.4. Duty cycle and frequency dependence 

5.5. Analysis of fin (channel) length scaling

5.6. Analysis of mean stress-recovery kinetics from small area devices

5.7. Process and dimension dependence of model parameters 

5.8. Analysis of end-of-life degradation

5.8.1. Comparison of empirical and physical methods

5.8.2. Impact of device architecture

5.9. Summary

6. Modeling of NBTI kinetics in RMG HKMG Si and SiGe bulk FinFETs

6.1. Introduction

6.2. Description of process splits

6.3. Analysis of measured data – impact of Ge% and N%

6.3.1. DC stress and recovery kinetics 

6.3.2. AC stress and recovery kinetics

6.3.3. Voltage and temperature dependence – DC stress

6.3.4. Voltage and temperature dependence – AC stress

6.3.5. Frequency and duty cycle dependence 

6.3.6. Anomalous frequency dependence 

6.4. Analysis of fin (channel) length and width scaling

6.5. Explanation of process dependence 

6.5.1. Process dependence of model parameters

6.5.2. Explanation of material (Ge%, N%) dependence

6.5.3. Similarity of FDSOI and FinFET parameters 

6.5.4. Explanation of dimension scaling

6.6. Analysis of end-of-life degradation 

6.6.1. Contribution of different subcomponents 

6.6.2. Comparison of empirical and physical methods

6.7. Summary

7. TCAD implementation of NBTI framework

7.1. Introduction

7.2. Implementation in TCAD framework

7.2.1. General overview

7.2.2. Process simulation

7.2.3. Bandstructure calculation and model parameter extraction

7.2.4. Device simulation – MSC framework

7.2.5. Device simulation – CE depassivation model

7.2.6. Transient Trap Occupancy Model   

7.3. Impact of physical models

7.3.1. Quantum potential

7.3.2. Mechanical strain

7.4. Validation using experimental data

7.4.1. Impact of Ge% in channel 

7.4.2. Impact of fin (channel) length scaling 

7.4.3. Impact of fin (channel) width scaling

7.5. Prediction of technology scaling

7.6. Summary  

8. NBTI in small area devices

8.1. Introduction

8.2. Experimental results

8.2.1. Stress and recovery kinetics

8.2.2. Distribution of statistical degradation

8.2.3. Time Dependent Defect Spectroscopy

8.2.4. Impact of single charge

8.3. Stochastic NBTI modeling framework

8.3.1. Generation and passivation of interface traps

8.3.2. Impact of H2 lock in 

8.3.3. Occupancy of interface traps

8.3.4. Hole trapping in pre-existing traps  

8.3.5. Calculation of percolation effect and charge impact

8.4. Comparison of stochastic and continuum models

8.5. Prediction of experimental data

8.6. Summary  

9. Analysis of digital logic circuit degradation

9.1. Introduction

9.2. Explanation of simulation flow

9.2.1. Implementation in TCAD framework

9.2.2. Implementation in SPICE framework

9.3. Comparison of TCAD and SPICE platforms

9.4. Analysis of RO degradation

9.5. Characterization of standard cells

9.6. Estimation of circuit degradation (DC worst case)

9.6.1. Conventional analysis scheme

9.6.2. Impact of subthreshold slope degradation

9.7. Impact of gate activity

9.7.1. Compact model description 

9.7.2. Analysis of random input patterns

9.7.3. Effective duty simulation

9.7.4. Verification of effective duty approach

9.8. Summary  

10. Statistical analysis of SRAM degradation

10.1. Introduction

10.2. Statistical compact NBTI model

10.3. Monte Carlo SPICE simulation setup

10.4. Estimation of SRAM parameter degradation

10.4.1. Read SNM

10.4.2. Hold SNM

10.4.3. Flip time

10.5. Analysis of high density and high speed cells

10.6. Impact of bit activity

10.7. Impact of time-zero and BTI correlation

10.8. Impact of subthreshold slope degradation

10.9. Summary  

O autorze

Souvik Mahapatra received his Bachelors and Masters degrees in Physics from Jadavpur University, Calcutta, India in 1993 and 1995 respectively, and PhD in Electrical Engineering from IIT Bombay, Mumbai, India in 1999. During 2000-2001, he was with Bell Laboratories, Lucent Technolgies, Murray Hill, NJ, USA. Since 2002 he is with IIT Bombay, and is currently the PK Kelkar Chair Professor in the Department of Electrical Engineering. His primary research interests are in the areas of semiconductor device characterization, modeling and simulation, and in particular, MOS transistor and Flash memory device scaling and reliability. He has interacted closely with major semiconductor industries in the world, and has contributed in several technologically relevant research topics such as MOS gate insulator scaling, Bias Temperature Instability and Hot Carrier Degradation in CMOS devices, CHISEL NOR Flash, SONOS NOR and NAND Flash memory devices. He has authored and co-authored more than 190 papers in peer reviewed journals and conferences and several book chapters, and delivered invited talks and tutorials in major international conferences around the world, including at the IEEE IEDM and IEEE IRPS. He has served as a distinguished lecturer of the IEEE EDS, chair of the IEEE EDS device reliability physics subcommittee, and in paper selection subcommittees and as session chairs in several IEEE conferences. He is a fellow of Institute of Electrical and Electronics Engineers (IEEE), Indian National Science Academy (INSA), Indian National Academy of Engineering (INAE) and Indian Academy of Sciences (IASc).