RTM Kernel Implementation on FPGA using High Level Synthesis Tool

ISBN-13: 9783659557651 / Angielski / Miękka / 2014 / 56 str.

Hussain Tassadaq;Haider Amna

Opis

The efficient data management is a key to the performance for many High Performance Computing (HPC) applications. The programmable devices normally support efficient utilization of data by providing a fixed architecture of caches or scratch pad memories. These caches or scratch pad memories are designed on the basis of few heuristics that are generic enough to provide varying degree of performance enhancement for various applications. However, the performance for applications having complex data accesses can still be improved by providing more customized memory layouts for those applications.

O autorze

Tassadaq is a Ph.D. researcher at the Universitat Politècnica de Catalunya, BarcelonaTech. For the period of his Ph.D., he is working as a research student in the Computer Science group at the Microsoft Barcelona Supercomputing Center Mircorsoft Research Center (BSCMRC).