ISBN-13: 9783847323761 / Angielski / Miękka / 2011 / 180 str.
The Set Partitioning in Hierarchical Trees (SPIHT) is modified and a new algorithm is developed, called Modified SPIHT (MSPIHT) using one list to store the co-ordinates of wavelet coefficients. When a coefficient of DWT is found as significant or insignificant, its last error bits will be omitted and rest of the bits will be outputted. MSPIHT is the low memory solution of SPIHT algorithm by eliminating the temporary list LSP and LIP. Absolute zerotree is a good solution of the rapid extension of LIS. The MATLAB simulation result shows that for coding a 512x512, gray-level image, MSPIHT reduce execution time at most 7 times and for decoding at most 11 times at low bit rate, saves at least 0.5625 MBytes of memory. The PSNR value of the reconstructed image using MSPIHT algorithm is reduced by 0.787% with respect to original SPIHT algorithm. This system is implemented on Altera EP2S60F1020C4 FPGA using the software Quartus II 6.0. The results from hardware implementation show that this design has speeded up at most 7129 times faster than that of the results obtained from MATLAB simulations; thereby making it highly promising for real-time and memory limited mobile communication.
The Set Partitioning in Hierarchical Trees (SPIHT) is modified and a new algorithm is developed, called Modified SPIHT (MSPIHT) using one list to store the co-ordinates of wavelet coefficients. When a coefficient of DWT is found as significant or insignificant, its last error bits will be omitted and rest of the bits will be outputted. MSPIHT is the low memory solution of SPIHT algorithm by eliminating the temporary list LSP and LIP. Absolute zerotree is a good solution of the rapid extension of LIS. The MATLAB simulation result shows that for coding a 512×512, gray-level image, MSPIHT reduce execution time at most 7 times and for decoding at most 11 times at low bit rate, saves at least 0.5625 MBytes of memory. The PSNR value of the reconstructed image using MSPIHT algorithm is reduced by 0.787% with respect to original SPIHT algorithm. This system is implemented on Altera EP2S60F1020C4 FPGA using the software Quartus II 6.0. The results from hardware implementation show that this design has speeded up at most 7129 times faster than that of the results obtained from MATLAB simulations; thereby making it highly promising for real-time and memory limited mobile communication.