Power-Aware Computer Systems: Second International Workshop, Pacs 2002 Cambridge, Ma, Usa, February 2, 2002, Revised Papers

ISBN-13: 9783540010289 / Angielski / Miękka / 2003 / 226 str.

Babak Falsafi; T. N. Vijaykumar; Babak Falsafi

Opis

WelcometotheproceedingsofthePower-AwareComputerSystems(PACS2002) workshopheld in conjunction with the 8th InternationalSymposium on High PerformanceComputerArchitecture(HPCA-8). Improvementsincomputers- temperformancehavebeenaccompaniedbyanalarmingincreaseinpowerand energydissipation, leading tohigher costandlowerreliabilityinallcomputer systemsmarketsegments. Thehigherpower/energydissipationhasalsosign- icantlyreducedbatterylife inportablesystems. Whilecircuit-leveltechniques continuetoreducepowerandenergy, alllevelsofcomputersystemsarebeing usedtoaddresspowerandenergyissues. PACS2002wasthesecondworkshopin itsseriestoaddresspower-/energy-awarenessatalllevelsofcomputersystems andbroughttogetherexpertsfromacademiaandindustry. Theseproceedingsincluderesearchpapersspanningawidespectrumof- eas in power-aware systems. We have grouped the papers into the following categories: (1)power-awarearchitectureandmicroarchitecture, (2)power-aware real-time systems, (3) power modeling and monitoring, and (4) power-aware operatingsystemsandcompilers. The?rstgroupofpapersproposepower-awaretechniquesfortheprocessor pipeline using adaptiveresizing of power-hungrymicroarchitecturalstructures andclockgating, andpower-awarecachedesignbyavoidingtagchecksin- riodswhenthetagshavenotchanged. Thisgroupalsoincludesideastoadapt energyandperformancedynamicallybydetectingregionsofapplicationatr- timewherethesupplyvoltagemaybescaledtoreducepowerwithabounded decrease in performance. Lastly, a paper on multiprocessor designs trades o? computingcapacityandfunctionalityforimprovedenergypercyclebysched- ing simple tasks on low-end and low-energy processorsand complex tasks on high-endprocessors. Thesecondgroupofpaperstargetreal-timesystemsincludingideasonal- complexityheuristicwhichschedulesreal-timetaskssuchthatnotaskmissesits deadlineandthetotalenergysavingsaremaximized. Theotherpapersinthis group(1)tunethesystem-levelparallelismtothecurrent-levelofpower/energy availabilityandoptimizethesystempowerutilization, and(2)performadaptive texturemappinginreal-time3Dgraphicssystemsbasedonamodelofhuman visualperceptiontoachievesigni?cantpowersavingswithoutnoticeableimage qualitydegradation. Thethirdgroupofpapersfocusonpowermodelingandmonitoringincluding statisticalpro?lingtodetectsoftwarehotspotsofpower, andusingPetriNetsto modelDRAMpowerpolicies. Thisgroupalsoincludesasimulatorforevaluating theperformanceandpowerofdynamicvoltagescalingalgorithms. Thelast groupconcentratesonOS and compilersfor lowpower. The ?rst paperproposesapplication-issueddirectivestosetthepowermodesindevices suchasadiskdrive. Thesecondpaperproposespoliciesforcluster-widepower VI Preface management. Thepoliciesemploycombinationsofdynamicvoltagescalingand turningonando?toreduceoverallclusterpower. PACS2002wasahighlysuccessfulforumduetothehigh-qualitysubmissions, theenormouse?ortsoftheprogramcommitteeandthekeynotespeaker, andthe attendees. WewouldliketothankRonnyRonenforanexcellentkeynotespeech, showingthetechnologicalscalingtrendsandtheirimpactonenergy/powerc- sumption in general-purposemicroprocessors, and pinpointing recentmicro- chitecturalstrategiestoachievemorepower-e?cientmicroprocessors. Wewould like to also thank Antonio Gonzalez, Andreas Moshovos, John Kalamatianos, andothermembersoftheHPCA-8organizingcommitteewhohelpedarrange forlocalaccomodationandpublicizetheworkshop. February2002 BabakFalsa?andT. N. Vijaykumar PACS2002 Program Committee BabakFalsa?, CarnegieMellonUniversity(co-chair) T. N. Vijaykumar, PurdueUniversity(co-chair) DaveA

Spis treści

Power-Aware Architecture/Microarchitecture.- Early-Stage Definition of LPX: A Low Power Issue-Execute Processor.- Dynamic Tag-Check Omission: A Low Power Instruction Cache Architecture Exploiting Execution Footprints.- A Hardware Architecture for Dynamic Performance and Energy Adaptation.- Multi-Processor Computer System Having Low Power Consumption.- Power-Aware Real-Time Systems.- An Integrated Heuristic Approach to Power-Aware Real-Time Scheduling.- Power-Aware Task Motion for Enhancing Dynamic Range of Embedded Systems with Renewable Energy Sources.- A Low-Power Content-Adaptive Texture Mapping Architecture for Real-Time 3D Graphics.- Power Modeling and Monitoring.- Energy-Driven Statistical Sampling: Detecting Software Hotspots.- Modeling of DRAM Power Control Policies Using Deterministic and Stochastic Petri Nets.- SimDVS: An Integrated Simulation Environment for Performance Evaluation of Dynamic Voltage Scaling Algorithms.- Power-Aware OS and Compilers.- Application-Supported Device Management for Energy and Performance.- Energy-Efficient Server Clusters.- Single Region vs. Multiple Regions: A Comparison of Different Compiler-Directed Dynamic Voltage Scheduling Approaches.