Power-Aware Computer Systems: First International Workshop, PACS 2000 Cambridge, MA, USA, November 12, 2000 Revised Papers

ISBN-13: 9783540423294 / Angielski / Miękka / 2001 / 158 str.

B. Falsafi;T.N. Vijaykumar

Opis

This text constitutes the thoroughly refereed post-proceedings of the First International Workshop on Power-Aware Computer Systems, PACS 2000, held in Cambridge, Massachusetts, USA, in November 2000. The 11 revised full papers presented were carefully reviewed, selected and revised for inclusion in the book. This book addresses power/energy-awareness at all levels of computer systems. The papers are organized in sections on power-aware microarchitectural/circuit techniques, application/compiler optimization, exploiting IPC/memory slack, and power/performance models and tools.

Spis treści

Power-Aware Microarchitectural/Circuit Techniques.- System-Level Design Methods for Low-Energy Architectures Containing Variable Voltage Processors.- Ramp Up/Down Functional Unit to Reduce Step Power.- An Adaptive Issue Queue for Reduced Power at High Performance.- Application/Compiler Optimizations.- Dynamic Memory Oriented Transformations in the MPEG4 IM1-Player on a Low Power Platform.- Exploiting Content Variation and Perception in Power-Aware 3D Graphics Rendering.- Compiler-Directed Dynamic Frequency and Voltage Scheduling.- Exploiting IPC/Memory Slack.- Cache-Line Decay: A Mechanism to Reduce Cache Leakage Power.- Dynamically Reconfiguring Processor Resources to Reduce Power Consumption in High-Performance Processors.- Power/Performance Models and Tools.- TEM2P2EST: A Thermal Enabled Multi-model Power/Performance ESTimator.- Power-Performance Modeling and Tradeoff Analysis for a High End Microprocessor.- A Comparison of Two Architectural Power Models.