Performance Analysis and Numerical Investigation of JLDG VeSFET

ISBN-13: 9786139997954 / Angielski / Miękka / 2019 / 200 str.

Tarun Chaudhary; Gargi Khanna

Opis

Exponential growth in portable electronic system requires more and more functionality to be united in modern VLSI silicon chip. Junctionless transistors, therefore, help the chip makers continue to make smaller and smaller devices in order to improve the performance of a chip. JLDG VeSFET offers a novel concept which not only provide new 3-D integration friendly manufacturing but a unique design paradigm which provides effective electrostatic control over the channel and supreme reduction of short channel effects. A complete analysis of the aforementioned device is presented here with a view to meet the needs of next generation IC technology.

O autorze

Chaudhary, Tarun
Tarun Chaudhary received B.E. degree in Electronics & Comm. Engineering from UIET, Panjab University, Chandigarh, in 2010. She received M.Tech degree in VDAT from NIT Hamirpur HP, India. She has completed her Ph.D. degree from NIT Hamirpur, India in year 2017. Her research interests include modeling and simulation of Nanoscale devices.