New Methods of Concurrent Checking

ISBN-13: 9781402084195 / Angielski / Twarda / 2008 / 182 str.

Michael Goessel; Vitaly Ocheretny

Opis

Computers are everywhere around us. We, for example, as air passengers, car drivers, laptop users with Internet connection, cell phone owners, hospital patients, inhabitants in the vicinity of a nuclear power station, students in a digital library or customers in a supermarket are dependent on their correct operation. Computers are incredibly fast, inexpensive and equipped with almost unimag- able large storage capacity. Up to 100 million transistors per chip are quite common today - a single transistor for each citizen of a large capital city in the world can be 2 easily accommodated on an ordinary chip. The size of such a chip is less than 1 cm . This is a fantastic achievement for an unbelievably low price. However, the very small and rapidly decreasing dimensions of the transistors and their connections over the years are also the reason for growing problems with reliability that will dramatically increase for the nano-technologies in the near future. Can we always trust computers? Are computers always reliable? Are chips suf- ciently tested with respect to all possible permanent faults if we buy them at a low price or have errors due to undetected permanent faults to be discovered by c- current checking? Besides permanent faults, many temporary or transient faults are also to be expected.

Spis treści

1 Introduction. 2 Physical Faults and Functional Errors. 2.1 Stuck-at Faults. 2.2 Bridging Faults. 2.3 CMOS Stuck-open and Stuck-on Faults. 2.4 Delay Faults. 2.5 Transient Faults. 2.6 Functional Error Model. 2.7 Output Dependencies. 2.8 Self-Testing and Self-Checking. 2.9 Faults and Errors in Submicron Technologies. 3 Principles of Concurrent Checking. 3.1 Duplication and Comparison. 3.2 Block Codes for Error Detection. 3.3 Parity and Group Parity Checking. 3.4 Odd and Even Error Detection. 3.5 Code-Disjoint Circuits. 3.6 Error Detection by Complementary Circuits. 3.7 General Method for the Design of Error Detection Circuits. 3.8 Self-Dual Error Detection. 3.9. Error Detection with Soft Error Correction. 4. Concurrent Checking for the Adders. 4.1 Basic Types of Adders. 4.2 Parity Checking for Adders. 4.3 Self-Checking Adders. References. Index.

Blurb

New Methods of Concurrent Checking is the ultimate reference to answer the question as to how the best possible state-of-the-art error detection circuits can be designed. The most effective methods of concurrent checking for digital circuits are comprehensively described which were developed in the last 15 years. Some of the methods are published for the first time. How concurrent checking can be combined with soft error correction is also shown for the first time. This book is invaluable in considering the design of reliable systems in the emerging Nanotechnologies with an associated growing number of transient faults.

Written by a team of two leading experts and two very successful young former PhD students, New Methods of Concurrent Checking describes new methods of concurrent checking, such as partial duplication, use of output dependencies, complementary circuits, self-dual parity, self-dual duplication and others. A special chapter demonstrates how the new general methods of concurrent checking can be more specifically applied to regular structures to obtain optimum results. This is exemplified for all types of adders up to 64 bits with a level of detail never before presented in the literature. The clearly written text is illustrated by about 100 figures.

New Methods of Concurrent Checking is approved in many university courses for graduate and undergraduate students, and it is of interest to students and teachers in electrical engineering and computer science, researchers and designers and all readers who are interested in the design and the understanding of reliable circuits and computers.