Multi-Net Optimization of VLSI Interconnect

ISBN-13: 9781461408208 / Angielski / Twarda / 2014 / 233 str.

Konstantin Moiseev;Avinoam Kolodny;Schmuel Wimer

Opis

This book covers layout design and layout migration methodologies for optimizing multi-net wire structures in advanced VLSI interconnects. Scaling-dependent models for interconnect power, interconnect delay and crosstalk noise are covered in depth, and several design optimization problems are addressed, such as minimization of interconnect power under delay constraints, or design for minimal delay in wire bundles within a given routing area. A handy reference or a guide for design methodologies and layout automation techniques, this book provides a foundation for physical design challenges of interconnect in advanced integrated circuits.

Spis treści

An Overview of the VLSI Interconnect Problem.- Interconnect Aspects in Design Methodology and EDA Tools.- Scaling Dependent Electrical Modeling of Interconnects.- Net-by-Net Wire Optimization.- Multi-Net Sizing and Spacing of Bundle Wires.- Multi-net Sizing and Spacing in General Layouts.- Interconnect Optimization by Net Ordering.- Layout Migration.- Future Directions in Interconnect Optimization.

O autorze

Konstantin Moiseev received the B.Sc., M.Sc. in Computer Engineering and Ph.D. in Electrical Engineering from the Technion – Israel Institute of Technology, Haifa, Israel in 2001, 2006 and 2011, respectively. Since 2006 he has been working with Intel Israel Design Center, Haifa, Israel. His general interests include computer-aided design systems, combinatorial optimization, heursitic methods, VLSI system design and interconnect design.

Avinoam Kolodny is an associate professor of electrical engineering at Technion –Israel Institute of Technology. He joined Intel after completing his doctorate in microelectronics at the Technion in 1980. During twenty years with the company he was engaged in diverse areas including non-volatile memory device physics, electronic design automation and organizational development.  He pioneered static timing analysis of processors, served as Intel’s corporate CAD system architect at the introduction of logic synthesis, and was manager of Intel’s performance verification CAD group in Israel. He has been a member of the Faculty of Electrical Engineering at the Technion since 2000. His current research is focused primarily on interconnect issues in VLSI systems, covering all levels from physical design of wires to networks on chip and multi-core system architecture.

Shmuel Wimer received the B.Sc. and M.Sc. degrees in mathematics from Tel-Aviv University, Tel-Aviv, Israel, and the D.Sc. degree in electrical engineering from the Technion-Israel Institute of Technology, Haifa, Israel, in 1978, 1981 and 1988, respectively. He worked for thirty two years at industry in R&D, engineering and managerial positions. From 1999 to 2009 he was with Intel Design Center in Haifa Israel, where he was responsible for the development, implementation and execution of Intel's microprocessors physical layout design migration (aka Tick-Tock). Prior to that, he worked for IBM, National Semiconductor and Israeli Aerospace Industry (IAI). He is presently an Associate Professor with the Engineering Faculty of Bar-Ilan University, and an Associate Visiting Professor with the Electrical Engineering Faculty, Technion. He is interested in VLSI circuits and systems design optimization and combinatorial optimization.

Blurb

This book covers layout design and layout migration methodologies for optimizing multi-net wire structures in advanced VLSI interconnects. Scaling-dependent models for interconnect power, interconnect delay and crosstalk noise are covered in depth, and several design optimization problems are addressed, such as minimization of interconnect power under delay constraints, or design for minimal delay in wire bundles within a given routing area. A handy reference or a guide for design methodologies and layout automation techniques, this book provides a foundation for physical design challenges of interconnect in advanced integrated circuits.
 • Describes the evolution of interconnect scaling and provides new techniques for layout migration and optimization, focusing on multi-net optimization;
• Presents research results that provide a level of design optimization which does not exist in commercially-available design automation software tools;
• Includes mathematical properties and conditions for optimality of layout, describes and analyses algorithmic solutions, and supplements analysis with examples taken from state-of-the-art chips.

This book addresses an intriguing engineering challenge, namely the design of an enormous maze of wires, which run in about a dozen metal layers above billions of transistors in a modern processor. The physical insight, mathematical rigor and methodological approach described in the book, are essential for engineers and computer architects, as they develop new systems of ever-increasing complexity and migrate them to new generations of device technologies.  The Authors of this book didn’t only develop the academic methodologies, but actually developed CAD tools, and implemented their tools and methodologies to design VLSI chips. I had the privilege to work with them.

--Mooly Eden, Senior Vice President, Intel Corporation; President, Intel Israel

The speed, power, area, and reliability of high performance integrated circuits are determined by the on-chip interconnect. With the publication of this book, an important niche has been filled; that is local and global on-chip interconnect optimization. This book provides a theoretical basis for the practical design of the key issue in modern integrated circuits, the on-chip interconnect.

--Eby G. Friedman, Distinguished Professor, University of Rochester