Multi-Level Simulation for VLSI Design

ISBN-13: 9781461294016 / Angielski / Miękka / 2011 / 206 str.

D. D. Hill; D. R. Coelho

Opis

AND BACKGROUND 1. 1 CAD, Specification and Simulation Computer Aided Design (CAD) is today a widely used expression referring to the study of ways in which computers can be used to expedite the design process. This can include the design of physical systems, architectural environments, manufacturing processes, and many other areas. This book concentrates on one area of CAD: the design of computer systems. Within this area, it focusses on just two aspects of computer design, the specification and the simulation of digital systems. VLSI design requires support in many other CAD areas, induding automatic layout. IC fabrication analysis, test generation, and others. The problem of specification is unique, however, in that it i > often the first one encountered in large chip designs, and one that is unlikely ever to be completely automated. This is true because until a design's objectives are specified in a machine-readable form, there is no way for other CAD tools to verify that the target system meets them. And unless the specifications can be simulated, it is unlikely that designers will have confidence in them, since specifications are potentially erroneous themselves. (In this context the term target system refers to the hardware and/or software that will ultimately be fabricated. ) On the other hand, since the functionality of a VLSI chip is ultimately determined by its layout geometry, one might question the need for CAD tools that work with areas other than layout.

Spis treści

1. Introduction and Background.- 1.1. CAD, Specification and Simulation.- 1.2. Categories of Simulation.- 1.3. Performance-Analysis.- 1.4. Register-Level Simulation.- 1.5. Functional-Level Simulation.- 1.6. Gate-Level Simulation.- 1.7. Analog Simulation.- 1.8. Problems with the Existing Approach.- 1.9. Multi-Level Simulation.- 1.10. Genesis of ADLIB.- 1.11. Outline of This Book.- 2. Principles of Multi-Level Simulation.- 2.1. Structure and Behavior.- 2.2. Two Concepts of “Level”.- 2.3. Design Methodologies.- 2.4. Top-Down Methodology Enhanced with Simulation.- 2.5. Example: Data Acquisition System.- 2.6. Refinement of Design.- 2.7. Stimulating A Component.- 2.8. Importance of Nets.- 2.9. Summary.- 3. The ADLIB Language.- 3.1. Purpose of ADLIB.- 3.2. Pascal Control Constructs.- 3.3. Additional ADLIB Constructs.- 3.4. Designing an ADLIB Program.- 3.5. Types, Net Types and Type Checking.- 3.6. Type Checking of Nets.- 3.7. Data Types Available in ADLIB.- 3.8. Another Example: The Rs232 Interface.- 3.9. Contour Models.- 3.10. Packages and Modules.- 3.11. Global Identifiers.- 3.12. Net Types.- 3.13. Clocks.- 3.14. Subroutines.- 3.15. Component Type Definitions.- 3.16. The Heading of a Component Type Definition.- 3.17. Port Declarations in a Component Type Definition.- 3.18. Internal Signals.- 3.19. Standard Pascal Declarations.- 3.20. Subprocesses.- 3.21. The Main Body of a Component Type Definition.- 3.22. Static Structure of an ADLIB Program.- 3.23. Summary—How Languages are Defined.- 4. Examples of Designing with ADLIB.- 4.1. A Gate-Level Example.- 4.2. A High-Level Example.- 4.3. Modeling Software.- 4.4. Protocol Example Summary: Using ADLIB for Algorithm Debugging.- 4.5. Model and Algorithm Debugging.- 4.6. An Hierarchical Example.- 4.7. Summary—Multi-Level Simulation.- 5. Advanced Principles.- 5.1. Using Model Main Bodies.- 5.2. Driver Models.- 5.3. Wired-Gate and Register Models.- 5.4. Wired-Gate Insertion.- 5.5. States and Memories.- 5.6. Synchronous and Asynchronous Processing.- 5.7. Use of Concurrent Processes.- 5.8. Pointers in Net Values.- 5.9. Model Initialization.- 5.10. Checking Timing Constraints.- 5.11. Timing Verification Algorithm.- 5.12. Timing Assertion Input.- 5.13. Performance Comparison.- 5.14. Fault Simulation.- 5.15. Symbolic Simulation.- 6. Implementation.- 6.1. Why Study an Implementation?.- 6.2. Sequence of System Programs.- 6.3. Preprocessing ADLIB into Pascal.- 6.4. Converting Component Types into Procedures.- 6.5. Generating Code to Support Net Types.- 6.6. Samples of ADLIB Preprocessor Transformations.- 6.7. Discussion: Global Variables, Scoping and Information Hiding.- 6.8. Simulation.- 6.9. Basic Data Structures.- 6.10. Accessing and Updating Nets.- 6.11. Nets Stimulating Components.- 6.12. Event Scheduling.- 6.13. Before Time = Zero.- 6.14. The Basic Event Cycle and its Efficiency.- 6.15. Interactive Support.- 6.16. Alternative Structures.- 6.17. Summary.- 7. Conclusion.- 7.1. Summary: The Essence of ADLIB.- 7.2. Lessons Learned from the Original ADLIB.- 7.3. Trends in Hardware Description Languages.- 7.4. The VHDL Language.- 7.5. Future Work.- Appendix A. ADLIB Syntax.- A. 1. Low-Level Syntax.- A.2. Summary of Operators.- A.3. Predeclared Identifiers.- A.4. Reserved Words.- A.5. Backus-Naur Form.- A.6. Comments on Syntax.- Appendix B. Packages.- B.l. Rndpak.- Appendix C. Translator Examples.- Appendix D. Symbolic Simulation Support Routines.- Appendix E. Bibliography.- Appendix F. Index.