Modeling, Analysis and Optimization of Network-On-Chip Communication Architectures

ISBN-13: 9789400739574 / Angielski / Twarda / 2013 / 174 str.

Umit Ogras

Opis

Traditionally, design space exploration for Systems-on-Chip (SoCs) has focused on the computational aspects of the problem at hand. However, as the number of components on a single chip and their performance continue to increase, the communication architecture plays a major role in the area, performance and energy consumption of the overall system. As a result, a shift from computation-based to communication-based design becomes mandatory. Towards this end, network-on-chip (NoC) communication architectures have emerged recently as a promising alternative to classical bus and point-to-point communication architectures. In this dissertation, we study outstanding research problems related to modeling, analysis and optimization of NoC communication architectures. More precisely, we present novel design methodologies, software tools and FPGA prototypes to aid the design of application-specific NoCs.

Spis treści

Introduction.- Literature Survey.- Motivational Example: MPEG-2 Encoder Design.- Target NoC Platform.- NoCPerformance Analysis.- Application-specific NoC Architecture Custimization using Long-range Links.- Analysis and Optimization of Prediction-based Flow Control in Networks-on-Chip.- Design and Management of VFI Partition Networks-on-Chip.- Conclusion.- Bibliography.- Appendix A. Tools and FPGA prototype.- Appendix B. Experiments using the Single-chip Cloud Computer (SCC) Platform.

Blurb

Traditionally, design space exploration for Systems-on-Chip (SoCs) has focused on the computational aspects of the problem at hand. However, as the number of components on a single chip and their performance continue to increase, the communication architecture plays a major role in the area, performance and energy consumption of the overall system. As a result, a shift from computation-based to communication-based design becomes mandatory. Towards this end, network-on-chip (NoC) communication architectures have emerged recently as a promising alternative to classical bus and point-to-point communication architectures.

This book explores outstanding research problems related to modeling, analysis and optimization of NoC communication architectures. More precisely, we present novel design methodologies, software tools and FPGA prototypes to aid the design of application-specific NoCs.