Microarchitecture of Network-On-Chip Routers: A Designer's Perspective

ISBN-13: 9781493945580 / Angielski / Miękka / 2016 / 175 str.

Giorgos Dimitrakopoulos; Anastasios Psarras; Ioannis Seitanidis

Opis

This book offers an overview of network-on-chip router micro-architecture, the corresponding design opportunities and challenges, and existing solutions to overcome these challenges. Includes examples that highlight both regular and worst-case scenarios.

Spis treści

Introduction to network-on-chip design.- Link-level flow control and buffering.- Baseline switching modules and routers.- Arbitration logic.- Pipelined wormhole routers.- Virtual-channel flow control and buffering.- Baseline virtual-channel based switching modules and routers.- High-speed allocators for VC-based routers.- Pipelined virtual-channel-based routers.

Blurb

This book focuses on the microarchitecture of network-on-chip routers from a designer’s perspective, providing ready-to-use solutions for simple and more sophisticated design cases. All aspects of the design of a network-on-chip router, including flow control, buffering architectures, arbitration and allocation, as well as pipelined organizations, are presented in detail. The authors provide numerous detailed examples and practical abstract models, when necessary. Router micro-architectural options are presented in a step-by-step manner, beginning from basic design principles. Even highly sophisticated design alternatives are categorized and broken down to simpler pieces that can be understood easily and analyzed. This book is an invaluable reference for system, architecture, circuit, and EDA researchers and developers, who are interested in understanding the overall picture of network-on-chip routers' microarchitecture, the associated design challenges, and the available solutions.

 · Covers all aspects of the microarchitecture of Network-on-Chip routers;

· Justifies and explains every design choice that is presented in a ready-to-use manner following a designer’s perspective;

· Describes performance-enhancing features in a step-by-step manner;

·Includes detailed examples presenting the flow of information inside the router on a cycle-by-cycle basis, highlighting the operation of each part under regular or worst-case traffic scenarios.