Low Power Asynchronous Logic design for Viterbi Decoders

ISBN-13: 9786139851294 / Angielski / Miękka / 2018 / 56 str.

T. Kalavathi Devi Sakthivel; Sakthivel Palaniappan

Opis

This book discusses the design of asynchronous logic and its importance in digital design. Most of the decoders designed and fabricated today are synchronous. The problem of clock skew is a major challenge in the synchronous design. Alternatively, asynchronous systems are becoming familiar as they are not in need of global clock, as these systems are locally synchronized by means of communication protocols. Asynchronous VLSI architecture for a Viterbi decoder is designed using Quasi Delay Insensitive (QDI) templates and Differential Cascode Voltage Switch Logic (DCVSL). It gives an overview of asynchronous implementation.

O autorze

Sakthivel, T. Kalavathi Devi
Dr T. Kalavathi Devi completed her UG and PG in GCT, Coimbatore. Her areas of interest include VLSI Design, low power circuits, electronics system design. She has published papers in reputed journals and international conferences. She is a recipient of Best project guide award from ISTE New Delhi, also best researcher award from ASDF.