Low Leakage SRAM Memory

ISBN-13: 9786205517116 / Angielski / Miękka / 68 str.

Debasis Mukherjee

Opis

I present some techniques to decrease the gate and other leakage dissipation in Deep Sub-Micron SRAM memories. This book reviews detail SRAM operations. This book also reviews various transistor intrinsic leakage mechanisms, including weak inversion, drain-induced barrier lowering, gate-induced drain leakage, and gate oxide tunneling. Finally, the book explores different circuit techniques to reduce the leakage power consumption. The W/L ratios are calculated from the equations of current in transistors (Linear and Saturation mode) for smooth read-write operation of both 0 and 1. I use W1/W3 = 1.5 and W4/W6 = 1.5. I first designed conventional SRAM memory and observed leakage current in various technology. In 90 nm technology conventional SRAM shows a leakage current of 1.87nA at steady state. Data retention gated-ground cache (DGR-cache) method reduces the leakage current to 100pA. Drowsy cache method reduces the leakage current to 84pA.

O autorze

Dr. Debasis Mukherjee is son of late Sukumar Mukherjee and Late Sabita Mukherjee. He completed his 10th and 12th from Bankura Zilla School and Bankura Christian College respectively. He did his B.E. from Bankura Unnayani Institute of Engineering, M.Tech from C-DAC Noida and Ph.D. from Guru Gobind Singh Indraprastha University.