Low Jitter Adaptive B/W Charge Pump PLL » książka
Low Jitter Adaptive B/W Charge Pump PLL
ISBN-13: 9783848441921 / Angielski / Miękka / 2012 / 112 str.
The rising demand for high-speed I/O has created an increasingly noisy environment in which PLLs must function. PFDs are widely used for their extended tracking range, frequency-aided acquisition and low cost. These are accompanied with Charge pump to generate control signal suitable for the VCO. An adaptive bandwidth that tracks with the operating frequency helps sustain the best jitter performance of the PLL over a wide frequency range. This book explores the architectures of blocks which contribute for the low jitter adaptive bandwidth charge pump PLL. PLLs have wide applications for Frequency Synthesis, where the output of PLL is a multiple of the frequency of the input reference signal. For low jitter operation, proper architecture for each block of PLL is selected, modeled in MATLAB and simulated. The suitable test setup to analyze the performance of PFD, CP, VCO, FD and the complete PLL is created. The design input reference is 10MHz and produces 2.4GHz. The design incorporates modifications in identified architectures for better performance. The 0.18um CMOS technology supports up to 2GHz, but the Divide-by-240 circuit has been designed with specialty."
The rising demand for high-speed I/O has created an increasingly noisy environment in which PLLs must function. PFDs are widely used for their extended tracking range, frequency-aided acquisition and low cost. These are accompanied with Charge pump to generate control signal suitable for the VCO. An adaptive bandwidth that tracks with the operating frequency helps sustain the best jitter performance of the PLL over a wide frequency range. This book explores the architectures of blocks which contribute for the low jitter adaptive bandwidth charge pump PLL. PLLs have wide applications for Frequency Synthesis, where the output of PLL is a multiple of the frequency of the input reference signal. For low jitter operation, proper architecture for each block of PLL is selected, modeled in MATLAB and simulated. The suitable test setup to analyze the performance of PFD, CP, VCO, FD and the complete PLL is created. The design input reference is 10MHz and produces 2.4GHz. The design incorporates modifications in identified architectures for better performance. The 0.18µm CMOS technology supports up to 2GHz, but the Divide-by-240 circuit has been designed with specialty.
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