Logic Synthesis and Optimization

ISBN-13: 9780792393085 / Angielski / Twarda / 1993 / 375 str.

Tsutomu Sasao

Opis

Logic Synthesis and Optimization presents up-to-date research information in a pedagogical form. The authors are recognized as the leading experts on the subject. The focus of the book is on logic minimization and includes such topics as two-level minimization, multi-level minimization, application of binary decision diagrams, delay optimization, asynchronous circuits, spectral method for logic design, field programmable gate array (FPGA) design, EXOR logic synthesis and technology mapping. Examples and illustrations are included so that each contribution can be read independently. Logic Synthesis and Optimization is an indispensable reference for academic researchers as well as professional CAD engineers.

Recenzje

'....I would recommend this book to any graduate student, or practising digital system design engineer, who wishes to know more about the subject and perhaps even develop new algorithms of his or her own.' Microprocessors and Microsystems 18:8 1994

Spis treści

Preface. 1. A New Exact Minimizer for Two-Level Logic Synthesis. 2. A New Graph Based Prime Computation Technique. 3. Logic Synthesizers, the Transduction Method and Its Extension, SYLON. 4. Network Optimization Using Don't-Cares and Boolean Relations. 5. Multi-Level Logic Minimization of Large Combinatorial Circuits by Partitioning. 6. A Partitioning Method for Area Optimization by Tree Analysis. 7. A New Algorithm for 0-1 Programming Based on Binary Decision Diagrams. 8. Delay Models and Exact Timing Analysis. 9. Challenges to Dependable Asynchronous Processor Design. 10. Efficient Spectral Techniques for Logic Synthesis. 11. FPGA Design by Generalized Functional Decomposition. 12. Logic Synthesis with EXOR Gates. 13. AND-EXOR Expressions and Their Optimization. 14. A Generation Method for EXOR-Sum-of-Products Expressions Using Shared Binary Decision Diagrams. 15. A New Technology Mapping Method Based on Concurrent Factorization and Mapping. 16. Gate Sizing for Cell-Based Designs. Subject Index.