Leakage in Nanometer CMOS Technologies

ISBN-13: 9781441938268 / Angielski / Miękka / 2010 / 308 str.

Siva G. Narendra; Anantha P. Chandrakasan

Opis

Scaling transistors into the nanometer regime has resulted in a dramatic increase in MOS leakage (i.e., off-state) current. Threshold voltages of transistors have scaled to maintain performance at reduced power supply voltages. Leakage current has become a major portion of the total power consumption, and in many scaled technologies leakage contributes 30-50% of the overall power consumption under nominal operating conditions. Leakage is important in a variety of different contexts. For example, in desktop applications, active leakage power (i.e., leakage power when the processor is computing) is becoming significant compared to switching power. In battery operated systems, standby leakage (i.e., leakage when the processor clock is turned off) dominates as energy is drawn over long idle periods. Increased transistor leakages not only impact the overall power consumed by a CMOS system, but also reduce the margins available for design due to the strong relationship between process variation and leakage power. It is essential for circuit and system designers to understand the components of leakage, sensitivity of leakage to different design parameters, and leakage mitigation techniques in nanometer technologies. This book provides an in-depth treatment of these issues for researchers and product designers.

Spis treści

Taxonomy of Leakage: Sources, Impact, and Solutions.- Leakage Dependence on Input Vector.- Power Gating and Dynamic Voltage Scaling.- Methodologies for Power Gating.- Body Biasing.- Process Variation and Adaptive Design.- Memory Leakage Reduction.- Active Leakage Reduction and Multi-Performance Devices.- Impact of Leakage Power and Variation on Testing.- Case Study: Leakage Reduction in Hitachi/Renesas Microprocessors.- Case Study: Leakage Reduction in the Intel Xscale Microprocessor.- Transistor Design to Reduce Leakage.

O autorze

Readers acquire understanding of why leakage power components are becoming increasingly relevant in CMOS systems that use nanometer scale MOS devices. Leakage current sources at the MOS device level including sub-threshold and different types of tunneling are discussed in detail. The book will cover in detail promising solutions at the device, circuit, and architecture levels of abstraction. Since manifestation of these MOS device leakage components at the full chip level depends considerably on several aspects including the nature of the circuit block, its state, its application workload, and Process/Voltage/Temperature conditions, the sensitivity of the various MOS leakage sources to these conditions are explained from the first principles. Also treated are the resulting effects so the reader understands the effectiveness of leakage power reduction solutions under these different conditions. With case studies supplying real-world examples that reap the benefits of leakage power reduction solutions, the book highlights different device design choices that exist to mitigate increases in the leakage components as technology scales.