Introduction to Logic Design

ISBN-13: 9781420060942 / Angielski / Twarda / 2008 / 692 str.

Svetlana N. Yanushkevich; Vlad P. Shmerko

Opis

New design techniques are constantly being developed to meet the needs of advancing technology. Placing an emphasis on emerging contemporary design techniques, Introduction to Logic Design presents the fundamental theory and practice of logic design. This comprehensive book reviews important data structures and explains various techniques for manipulating them. In addition to providing suggestions for further study, each chapter features numerous design examples to illustrate methods along with concise summaries to highlight key concepts. Ideal for students, the text also includes over 300 homework problems and offers a solutions manual as well as lecture transparencies for instructors.

Spis treści

Preface
Design Process and Technology
Theory of logic design
Analysis and synthesis
Implementation technologies
Predictable technologies
Contemporary CAD of logic networks
Number Systems
Positional numbers
Counting in a positional number system
Basic arithmetic operations in various number systems
Binary arithmetic
Radix-complement representations
Techniques for conversion of numbers in various radices
Overflow
Residue arithmetic
Other binary codes
Redundancy and reliability
Graphical Data Structures
Graphs in discrete devices and systems design
Basic definitions
Tree-like graphs and decision trees
Algebra I: Boolean
Definition of Boolean algebra over the set {0, 1}
Boolean functions
Fundamentals of computing Boolean functions
Proving the validity of Boolean equations
Gates
Local transformations
Observability and validity check
Fundamental Expansions
Shannon expansion with respect to a single variable
Shannon expansion with respect to a group of variables
Shannon expansion with respect to all variables (boundary case)
Other forms of Shannon expansion
Boolean difference
Controllability and observability for logic networks
The logic Taylor expansion
Graphical representation of Shannon expansion
Boolean Data Structures
The data structure types
The relationships between data structures
The truth table
K-map
Cube data structure
Hypercube data structure
Logic networks
Network of threshold gates
Binary decision trees
Decision diagrams
Properties of Boolean Functions (Optional)
Self-dual Boolean functions
Monotonic Boolean functions
Linear functions
Symmetric functions
Universal set of functions
Optimization I: Algebraic and K-Maps
The minterm and maxterm expansions: algebraic forms
Optimization of Boolean functions in algebraic forms
Implementing SOP expression using the library of gates
Minimization of Boolean functions using K-maps
Quine–McCluskey algorithm
Boolean function minimization using decision diagrams
Optimization II: Decision Diagrams
Optimization of Boolean functions using decision trees
Decision diagrams for symmetric Boolean functions
Measurement of efficiency of decision diagrams
Representation of multi-output Boolean functions
Embedding decision diagrams into lattice structures
Algebra II: Polynomial
Algebra of the polynomial forms
GF(2) algebra
Relationship between standard SOP and polynomial forms
Local transformations for EXOR networks
Factoring of polynomials
Validity check for EXOR networks
Manipulation of Polynomial Expressions
Fixed and mixed polarity polynomial forms
Computing the coefficients of polynomial forms
Decision Diagrams for Polynomial Forms (Optional)
Function of the nodes
Techniques for the functional decision trees construction
Functional decision tree reduction
Standard Modules of Combinational Networks
Data transfer logic
Implementation of Boolean functions using multiplexers
Demultiplexers
Decoders
Implementation of Boolean functions using decoders
Encoders
Combinational Logic Network Design
Design example: binary adder
Design example: the two-bit magnitude comparator
Design example: BCD adder
Verification problem
Decomposition
Error detection and error correction logic networks
Standard Modules of Sequential Logic Networks
Physical phenomena of storing data
Basic principles
Data structures for sequential logic networks analysis and synthesis
Latches
Flip-flops
Registers
Counters
Decision diagrams in modeling of standard sequential elements
Memory and Programmable Devices
Gate array concept
Random-access memory
Read-only memory
Memory expansion
Programmable logic
Field-programmable gate arrays
Sequential Logic Network Design
Mealy and Moore models of sequential networks
Data structures for analysis of sequential networks
Analysis of sequential networks with various types of flip-flops
Techniques for synthesis of sequential networks
State table reduction and assignment
Decision diagrams in modeling of sequential networks
Design for Testability
Fault detection and Boolean differences
Fault models based on functional decision diagrams
Detection of stuck at faults
Path sensitizing
Random tests
Design for testability techniques
Index
An Introduction, a Summary, Further Study, Solutions to Practice Problems, and Problems appear in each chapter.

O autorze

Svetlana N. Yanushkevich, Vlad P. Shmerko