Ingredients for Successful System Level Design Methodology

ISBN-13: 9781402084713 / Angielski / Twarda / 2008 / 208 str.

Hiren D. Patel; Sandeep Kumar Shukla

Opis

ESL or Electronic System Level is a buzz word these days, in the electronic design automation (EDA) industry, in design houses, and in the academia. Even though numerous trade magazine articles have been written, quite a few books have been published that have attempted to de?ne ESL, it is still not clear what exactly it entails. However, what seems clear to every one is that the Register Transfer Level (RTL) languages are not adequate any more to be the design entry point for today s and tomorrow s complex electronic system design. There are multiple reasons for such thoughts. First, the c- tinued progression of the miniaturization of the silicon technology has led to the ability of putting almost a billion transistors on a single chip. Second, applications are becoming more and more complex, and integrated with c- munication, control, ubiquitous and pervasive computing, and hence the need for ever faster, ever more reliable, and more robust electronic systems is pu- ing designers towards a productivity demand that is not sustainable without a fundamental change in the design methodologies. Also, the hardware and software functionalities are getting interchangeable and ability to model and design both in the same manner is gaining importance. Given this context, we assume that any methodology that allows us to model an entire electronic system from a system perspective, rather than just hardware with discrete-event or cycle based semantics is an ESL method- ogy of some kind."

Spis treści

Preface. Acknowledgments. 1 Introduction. 1.1 Motivation. 1.2 Organization 2 Related Work. 2.1 System Level Design Languages and Frameworks. 2.2 Verification of SystemC Designs. 2.3 Reflection and Introspection. 2.4 Service-orientation. 3 Background. 3.1 Fidelity, Expressiveness and Multiple Models of Computation. 4 Behavioral Hierarchy with Hierarchical FSMs (HFSMs). 4.1 Behavioral Modeling versus Structural Modeling. 4.2 Finite State Machine Terminology. 4.3 Requirements for Behavioral Hierarchy in SystemC. 4.4 Execution Semantics for Hierarchical FSMs. 4.5 Implementation of Hierarchical FSMs. 4.6 Modeling Guidelines for HFSM. 4.7 HFSM Example: Power Model. 5 Simulation Semantics for Heterogeneous Behavioral Hierarchy. 5.1 Abstract Semantics. 5.2 Basic Definitions. 5.3 Execution Semantics for Starcharts. 5.4 Our Execution Semantics for Hierarchical FSMs. 5.5 Implementing Heterogeneous Behavioral Hierarchy. 5.6 Examples. 6 Bluespec ESL and its Co-simulation with SystemC DE. 6.1 Advantages of this Work. 6.2 Design Flow. 6.3 BS-ESL Language. 6.4 BS-ESL Execution. 6.5 An Example Demonstrating BS-ESL and SystemC Integration. 6.6 Summary. 6.7 Interoperability between SystemC and BS-ESL. 6.8 Problem Description. 6.9 Solution: Our Interoperability Technique. 6.10 Summary. 7 Model-driven Validation of SystemC Designs. 7.1 Overview of this Work. 7.2 Design Flow. 7.3 Results: Validation of FIFO, FIR and GCD. 7.4 Our Experience. 7.5 Evaluation of this Approach. 7.6 Summary. 8 Service-orientation for Dynamic Integration of Multiple Tools. 8.1 CARH’s Capabilities. 8.2 Issues and Inadequacies of Current SLDLs and Dynamic Validation Frameworks. 8.3 Our Generic Approach to Addressing these Inadequacies. 8.4 CARH’s Software Architecture. 8.5 Services Rendered by CARH. 8.6Usage Model of CARH. 8.7 Simulation Results. 8.8 Our Experience with CARH. 9 Summary Evaluations. 9.1 Modeling and Simulating Heterogeneous Behaviors in SystemC. 9.2 Validating Corner Case Scenarios for SystemC. 9.3 Dynamic Integration of Multiple Tools. 10 Conclusion and Future work. A Parsing SystemC using C/C++ Front-end Compiler. A.1 Tool Flow. A.2 Parsing SystemC. B Eclpise-based Plugin for a SystemC IDE. B.1 Project Overview. B.2 SystemC IDE Feature. B.3 SystemC IDE Plug-in. B.4 Setting up the SystemC IDE. B.5 A Little About Implementation. References.

Blurb

System Level Design (SLD) and Electronic System Level (ESL) Design are buzzwords of today‘s Electronic Design Automation industry. The idea is to raise the level of abstraction of the design entry for future hardware systems beyond the register transfer level. This is necessitated by the increasing complexity of the systems, co-dependence between hardware and software, the immense gate count available on a single chip, the relatively slower growth in designer productivity, and decreasing design turn around time. Even though a number of languages and design environments have been proposed in the last few years which include SystemC, Bluespec, SpecC, and System Verilog, etc., none of these satisfy our wish list for a successful system level design language or framework. We want languages and frameworks which will enable us to model heterogeneous system-on-chips. These can be best captured by a language capable of expressing and co-simulating multiple models of computation. Also, we want to model behavior rather than structure, and want our SLD languages to support simulation of behavioral hierarchy, rather than structural ones available in the existing languages. We also want easier integration of frameworks and tools from various vendors and open source tools that not only support design, verification, dynamic waveform viewing, coverage driven dynamic test generation within the same framework, but also allows dynamic enabling or disabling some of the tools from the integrated framework to speed up simulation as needed. We also want open source Eclipse plug-in for SystemC or similar ESL languages. We want the ability for dynamic reflection and introspection from a running simulation to provide us with information about simulation state and accordingly generate tests dynamically to fulfill coverage goals. Ingredients for Successful System Level Design Methodology discusses these wish lists, and provides detailed discussions on how our prototype implementations provide us with these much desired features.