Improved performance of on-chip data interconnects

ISBN-13: 9786202672481 / Angielski / Miękka / 2020 / 156 str.

Chennakesavulu Maddiraala; T. Jayachandra Prasad; V. Sumalatha

Opis

Trading off the reliability, crosstalk delay and power dissipation on on-chip buses are challenging issue for the design community in Deep Sub Micron (DSM) and very deep beneath Micron Technologies (VDSM). To improve the overall system performance it is necessary to reduce and scaling technology to control these effects data on-chip interconnects. Error Correcting Codes (ECC) have been used on the data buses to increase the reliability of the data transfer on the bus on-chip data with penalty of overhead power, delay and area. The dynamic power dissipation of interconnects depends on supply voltage, operating clock frequency, load capacitance and switching activity. All the parameters which influence the dynamic power dissipation are technology dependent except switching activity. Dynamic power dissipation has been reduced by reducing the switching activity. The switching activity has been reduced by adopting a data encoding technique on data interconnects. Encoding the data on it interconnects the promising technique to decrease the dynamic power dissipation and total on-chip delay on the buses and hence overall system performance can be increased.

O autorze

Maddiraala, Chennakesavulu
He has completed B.Tech in ECE from JNTUH in 2003, M.Tech in Embedded Systems from JNTUA in 2010. He has completed Ph.D from JNTUA in 2020. He has 16 years of teaching experience and published 20+ national and international journals and conferences. His interested research areas are Low power VLSI design and Data encoding techniques.