IMPLEMENTATION OF HIGH PERFORMANCE 32-BIT RISC CORE ARCHITECTURE

ISBN-13: 9786206183303 / Angielski / Miękka / 84 str.

CHANDRA SHAKER ARRABOTU; M RAJANI; D RAVI CHANDAN

Opis

This book is about designing a RISC processor using pipelined architecture. 5-stage pipelining is used to improve the speed of the operation. The 5 stages are Fetch, Decode, Execute, Memory and Write Back. The design process includes various low power techniques at architectural level which proves that this methods is more efficient than Back-end low power reduction techniques. Low power embedded processors are used in a wide variety of applications including cars, phones, digital cameras, printers, and other such devices. The reason for their wide use is that they are small therefore, they do not take up much die area and are cost effective to fabricate. Low power consumption helps to reduce the heat dissipation, lengthen battery life and increase device reliability.

O autorze

Chandra Shaker Arrabotu is currently working as Assistant Professor in Department of Electronics and Telematics Engineering, G. Nararayanamma Institute of Technology and Science (for Women), Hyderabad. His research interests include Internet of Things, Multi-access Edge Computing, Machine Learning, Embedded Systems.