High-performance Video Decoding using Graphics Processing Units

ISBN-13: 9783746731001 / Angielski / Miękka / 2018 / 176 str.

Biao Wang

Opis

The increasing demand of decoding high-quality videos can lead to a challenging com-putational requirement for conventional Central Processing Unit (CPU) architectures.Graphics Processing Units (GPUs) in general provide higher computational powerthan CPUs. Efficient GPU execution, however, requires massive parallelism and little ex-ecuting divergence, two criteria are not fully met by all video decoding kernels. This thesisexploits how GPUs can be effectively used in video decoding applications. The challengesinclude proper workload distribution between the CPU and GPU, task optimizations ontwo heterogeneous devices, and efficient communication between them.A complete parallel HEVC decoder was proposed for heterogeneous CPU+GPUsystems. We exploited available decoding parallelism on the CPU, GPU, and between thetwo devices simultaneously. On top of the parallel design, two workload balancing schemeswere implemented, in order to adapt computation resource variation on CPU and GPU.In addition, an energy measurement module was developed for energy efficiency analysis.Evaluated results showed that suitable decoding kernels can be accelerated substan-tially (up to 28.2×) on GPUs at the kernel level. At the application level, using GPUarchitecture can provide significant acceleration when only a low number (1 to 8) of CPUcores are available. On a system consisting of an NVIDIA Titan X Maxwell GPU and anIntel Xeon E5-2699v3 CPU, with four CPU cores, the proposed HEVC decoder delivers167 frames per second for 4K videos, corresponding to a speedup of 2.2× over the state-of-the-art CPU decoder using four CPU cores. When more CPU cores (8) are employed,the benefit of using GPU vanishes and the performance is eventually outperformed by theCPU decoder due to GPU overloading. With respect to energy, because of its high powerconsumption GPU architecture is not as efficient as the CPU for HEVC decoding.

O autorze

Wang, BiaoBiao Wang received the M.S. degree in Computer Application Technology in July 2010 and Bachelor degree in Computer Software Technology in July 2007, both from University of Electronic Science and Technology of China (UESTC), ChengDu, China. Since Oct 2010, he joined the Embedded Systems Architecture as a PhD student with scholarship from China Scholarship Council (CSC).His research is focused on video decoding using Graphic Processing Units (GPUs). He is experienced in high performance video decoding on heterogeneous systems with CPU and GPU. Some of these works are published in international conferences and prestigious journals.