Hardware Specification, Verification and Synthesis: Mathematical Aspects: Mathematical Sciences Institute Workshop. Cornell University Ithaca, New Yor

ISBN-13: 9780387972268 / Angielski / Miękka / 1990 / 404 str.

Cornell University; Miriam Leeser; Geoffrey Brown

Opis

Current research into formal methods for hardware design is presented in the papers in this volume. The goal of research in this area is to develop methods of improving the design process and the quality of the resulting designs.

Spis treści

Design for verifiability.- Verification of synchronous circuits by symbolic logic simulation.- Constraints, abstraction, and verification.- Formalising the design of an SECD chip.- Reasoning about state machines in higher-order logic.- A mechanically derived systolic implementation of pyramid initialization.- Behavior-preserving transformations for high-level synthesis.- From programs to transistors: Verifying hardware synthesis tools.- Combining engineering vigor with mathematical rigor.- Totally verified systems: Linking verified software to verified hardware.- What's in a timing discipline? Considerations in the specification and synthesis of systems with interacting asynchronous and synchronous components.- Complete trace structures.- The design of a delay-insensitive microprocessor: An example of circuit synthesis by program transformation.- Manipulating logical organization with system factorizations.- The verification of a bit-slice ALU.- Verification of a pipelined microprocessor using clio.- Verification of combinational logic in Nuprl.- Veritas+: A specification language based on type theory.- Categories for the working hardware designer.