Hardware Protection Through Obfuscation

ISBN-13: 9783319840680 / Angielski / Miękka / 2018 / 349 str.

Domenic Forte; Swarup Bhunia; Mark M. Tehranipoor

Spis treści

Part 1: Hardware Obfuscation Preliminaries.- Introduction to Hardware Obfuscation: Motivation, Methods and Evaluation.- VLSI Test and Hardware Security Background for Hardware Obfuscation.- Part 2: Logic-based Hardware Obfuscation.- Logic Encryption.- Gate Camouflaging-based Obfuscation.- Permutation-Based Obfuscation.- Protection of Assets from Scan Chain Vulnerabilities through Obfuscation.- Part 3: Finite State Machine (FSM) Based Hardware Obfuscation.- Active Hardware Metering by Finite State Machine Obfuscation.- State Space Obfuscation and its Application in Hardware Intellectual Property Protection.- Structural Transformation-based Obfuscation.- Part 4: Hardware Obfuscation Based on Emerging Integration Approaches.- Part IV Hardware Obfuscation Based on Emerging Integration Approaches.- Split Manufacturing.- Obfuscated Built-in Self Authentication.- 3D/2.5D IC based Obfuscation.- Part 5: Other Hardware Obfuscation Building Blocks.- Obfuscation and Encryption for Securing Semiconductor Supply Chain.

O autorze

Domenic Forte received his B.S. degree in Electrical Engineering from Manhattan College, Riverdale, NY, USA, in 2006, and the M.S. and Ph.D. degrees in Electrical Engineering from the University of Maryland, College Park, MD, USA, in 2010 and 2013, respectively. Currently, he is an Assistant Professor with the Electrical and Computer Engineering Department at University of Florida. His research is primarily focused on the domain of hardware security and includes investigation of hardware security primitives, hardware Trojan detection and prevention, security of the electronics supply chain, hardware obfuscation, and anti-reverse engineering. His work has been recognized through several best paper awards and nominations from venues such as International Symposium on Hardware Oriented Security and Trust (HOST), Design Automation Conference (DAC), and Adaptive Hardware Systems (AHS). He is a coauthor of the book “Counterfeit Integrated Circuits- Detection and Avoidance”. He is currently serving as an Associate Editor for the Journal of Hardware and Systems Security (HaSS) and was previously Guest Editor of the IEEE Computer Special Issue on “Supply Chain Security for Cyber-Infrastructure.” He is also serving on the organizing committees of HOST and AsianHOST as well as the technical program committees of various noteworthy conferences and workshops.

Swarup Bhunia received his B.E. (Hons.) from Jadavpur University, Kolkata, India, and the M.Tech. degree from the Indian Institute of Technology (IIT), Kharagpur. He received his Ph.D. from Purdue University, IN, USA, in 2005. Currently, Dr. Bhunia is a professor in the department of Electrical and Computer Engineering at University of Florida, Gainesville, FL, USA. Earlier, Dr. Bhunia has served as the T. and A. Schroeder associate professor of Electrical Engineering and Computer Science at Case Western Reserve University, Cleveland, OH, USA. He has over ten years of research and development experience with over 200 publications in peer-reviewed journals and premier conferences and four books (three edited) in the area of VLSI design, CAD and test techniques. His research interests include low power and robust design, hardware security and trust, adaptive nanocomputing and novel test methodologies. He has worked in the semiconductor industry on RTL synthesis, verification, and low power design for about three years. Dr. Bhunia received IBM Faculty Award (2013), National Science Foundation (NSF) career development award (2011), Semiconductor Research Corporation (SRC) technical excellence award (2005), best paper award in International Conference on VLSI Design (VLSI Design 2012), best paper award in International Conference on Computer Design (ICCD 2004), best paper award in Latin American Test Workshop (LATW 2003), and best paper nomination in Asia and South Pacific Design Automation Conference (ASP-DAC 2006) and in Hardware Oriented Test and Security (HOST 2010), nomination for John S. Diekhoff Award, Case Western Reserve University (2010) and SRC Inventor Recognition Award (2009).

Mark M. Tehranipoor is currently the Intel Charles E. Young Professor in Cybersecurity at the Department of Electrical and Computer Engineering, the University of Florida. His current research projects include: hardware security and trust, electronics supply chain security, counterfeit IC detection and prevention, and reliable and testable VLSI design. Prof. Tehranipoor has published over 300 journal articles and refereed conference papers and has given more than 160 invited talks and keynote addresses since 2006. In addition, he has published six books and ten book chapters. His projects are sponsored by both the industry and the Government. Prior to joining University of Florida, Dr. Tehranipoor served as the founding director of the Center for Hardware Assurance, Security, and Engineering (CHASE) and the Comcast Center of Excellence in Security Innovation (CSI) at the University of Connecticut. Prof. Tehranipoor is a Senior Member of the IEEE, Golden Core Member of IEEE Computer Society, and Member of ACM and ACM SIGDA. He is also a member of Connecticut Academy of Science and Engineering (CASE).

Blurb

This book introduces readers to various threats faced during design and fabrication by today’s integrated circuits (ICs) and systems. The authors discuss key issues, including illegal manufacturing of ICs or “IC Overproduction,” insertion of malicious circuits, referred as “Hardware Trojans”, which cause in-field chip/system malfunction, and reverse engineering and piracy of hardware intellectual property (IP). The authors provide a timely discussion of these threats, along with techniques for IC protection based on hardware obfuscation, which makes reverse-engineering an IC design infeasible for adversaries and untrusted parties with any reasonable amount of resources. This exhaustive study includes a review of the hardware obfuscation methods developed at each level of abstraction (RTL, gate, and layout) for conventional IC manufacturing, new forms of obfuscation for emerging integration strategies (split manufacturing, 2.5D ICs, and 3D ICs), and on-chip infrastructure needed for secure exchange of obfuscation keys- arguably the most critical element of hardware obfuscation.