From Variability Tolerance to Approximate Computing in Parallel Integrated Architectures and Accelerators

ISBN-13: 9783319852393 / Angielski / Miękka / 2018 / 197 str.

Abbas Rahimi; Luca Benini; Rajesh K. Gupta

Spis treści

Introduction.- Part 1. Predicting and Preventing Errors.- Instruction-Level Tolerance.- Sequence-Level Tolerance.- Procedure-Level Tolerance.- Kernel-Level Tolerance.- Hierarchically Focused Guardbanding.- Part 2. Detecting and Correcting Errors.- Work-Unit Tolerance.- Memristive-Based Associative Memory for Error Recovery.- Part 3. Accepting Errors.- Accuracy-Configurable OpenMP.- An Approximation Workflow for Exploiting Data-Level Parallelism in FPGA Acceleration.- Memristive-Based Associative Memory for Approximate Computational Reuse.- Spatial and Temporal Memoization.- Outlook.

O autorze

Abbas Rahimi is currently a Postdoctoral Scholar in the Department of Electrical Engineering and Computer Sciences at the University of California Berkeley, Berkeley, CA, USA. He is a member of the Berkeley Wireless Research Center and collaborating with UC Berkeley’s Redwood Center for Theoretical Neuroscience. Rahimi has a B.S. in computer engineering from the University of Tehran, Tehran, Iran (2010) and an M.S. and a Ph.D. in computer science and engineering from the University of California San Diego, La Jolla, CA, USA (2015). His research interests include brain-inspired computing, approximate computing, massively parallel integrated architectures, embedded systems and software with an emphasis on improving energy efficiency and robustness. His doctoral dissertation has been selected to receive the 2015 Outstanding Dissertation Award in the area of "New Directions in Embedded System Design and Embedded Software" from the European Design and Automation Association. He has published more than 40 papers in top tier conferences and journals, and received the Best Paper Candidate at 50th IEEE/ACM Design Automation Conference.

Luca Benini is a Professor of Digital Circuits and Systems at ETH Zurich, Switzerland, and is also a Professor at University of Bologna, Italy. He has a PhD in Electrical Engineering from Stanford University (1997). His research interests are in energy-efficient system design and multicore SoC design. He is a Fellow of both IEEE and ACM, and  member of the Academia Europea.

Rajesh K. Gupta is a Professor of Computer Science and Engineering at the University of California San Diego (UCSD), La Jolla, CA, USA and holds the Qualcomm endowed chair. Gupta has a BTech in electrical engineering from the Indian Institute of Technology, Kanpur, India (1984), an MS in electrical engineering and computer science from the University of California Berkeley, Berkeley, CA, USA (1986), and a PhD in electrical engineering from Stanford University, Stanford, CA, USA (1994). He is a Fellow of both IEEE and ACM.

Blurb

This book focuses on computing devices and their design at various levels to combat variability.  The authors provide a review of key concepts with particular emphasis on timing errors caused by various variability sources. They discuss methods to predict and prevent, detect and correct, and finally conditions under which such errors can be accepted; they also consider their implications on cost, performance and quality. Coverage includes a comparative evaluation of methods for deployment across various layers of the system from circuits, architecture, to application software. These can be combined in various ways to achieve specific goals related to observability and controllability of the variability effects, providing means to achieve cross layer or hybrid resilience.

• ·         Covers challenges and opportunities in identifying microelectronic variability and the resulting errors at various layers in the system abstraction;
  
• ·         Enables readers to assess how various levels of circuit and system design can mitigate the effects of variability;
  
• ·         Demonstrates overall system architecture of what is now called “approximate computing” paradigm in massively parallel integrated architectures and accelerators.