FPGA Implementation of Priority Rank Based Routing Algorithm : Low Area in NOC

ISBN-13: 9783330043459 / Angielski

Parul Anand

Opis

Network on chip has become a promising solution pertaining to developing a large number of cores on the chip to obtain top rated. This built in framework redundancy regarding NoC provides the potential to design the fault-tolerant routing protocol to enhance this trustworthiness. Network on chip is definitely an interconnection concerning many control aspects and routers. There are several alternatives for the occurrence of faults in the network. These kinds of faults degrade the performance of the network. Some fault-tolerant algorithms are proposed to support special cases of faults, such as one-faulty routers, convex or concave regions. These algorithms either disable the healthy components or require a large number of virtual channels to avoid deadlock.

O autorze

Anand, Parul
Parul Anand has over 4 years of experience in teaching & training students and professionals in various reputed organizations. She began working on research in 2015. She received degree in Master of Technology in VLSI Design under Electronics & Communication stream. Her research interest is in various topics related to Communication & VLSI Design.