FPGA Based Network Security Architecture for High Speed Networks » książka
FPGA Based Network Security Architecture for High Speed Networks
ISBN-13: 9783845414799 / Angielski / Miękka / 2011 / 80 str.
Cryptography and Network Security in high speed networks demands for specializedhardware in order to match up with the network speed. These hardwaremodules are being realized using reconfigurable FPGA technology to supportheavy computation. Our work is mainly based on designing an efficient architecturefor a cryptographic module and a network intrusion detection system for ahigh speed network. All the designs are coded using VHDL and are synthesizedusing Xilinx ISE for verifying their functionality. Virtex II pro FPGA is chosenas the target device for realization of the proposed design. The Network IntrusionDetection System (NIDS) module is designed for scanning suspicious patterns indata packets incoming to the network. Scanning a data packet against multiplepatterns in quick time is a highly computational intensive task. The design goal is to increasethe data conversion rate i.e the throughput to a substantial value so thatthe design can be used as a separate hardware module in high speed network applications.
Cryptography and Network Security in high speed networks demands for specializedhardware in order to match up with the network speed. These hardwaremodules are being realized using reconfigurable FPGA technology to supportheavy computation. Our work is mainly based on designing an efficient architecturefor a cryptographic module and a network intrusion detection system for ahigh speed network. All the designs are coded using VHDL and are synthesizedusing Xilinx ISE for verifying their functionality. Virtex II pro FPGA is chosenas the target device for realization of the proposed design. The Network IntrusionDetection System (NIDS) module is designed for scanning suspicious patterns indata packets incoming to the network. Scanning a data packet against multiplepatterns in quick time is a highly computational intensive task. The design goal is to increasethe data conversion rate i.e the throughput to a substantial value so thatthe design can be used as a separate hardware module in high speed network applications.
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