Digital VLSI Design and Simulation with Verilog

ISBN-13: 9781119778042 / Angielski / Twarda / 2021 / 224 str.

Govind S Patel

Spis treści

Preface xiAbout the Authors xiii1 Combinational Circuit Design 11.1 Logic Gates 11.1.1 Universal Gate Operation 31.1.2 Combinational Logic Circuits 51.2 Combinational Logic Circuits Using MSI 61.2.1 Adders 61.2.2 Multiplexers 121.2.3 De-multiplexer 141.2.4 Decoders 151.2.5 Multiplier 171.2.6 Comparators 181.2.7 Code Converters 191.2.8 Decimal to BCD Encoder 20Review Questions 21Multiple Choice Questions 22Reference 232 Sequential Circuit Design 252.1 Flip-flops (F/F) 252.1.1 S-R F/F 252.1.2 D F/F 262.1.3 J-K F/F 262.1.4 T F/F 282.1.5 F/F Excitation Table 292.1.6 F/F Characteristic Table 292.2 Registers 312.2.1 Serial I/P and Serial O/P (SISO) 312.2.2 Serial Input and Parallel Output (SIPO) 312.2.3 Parallel Input and Parallel Output (PIPO) 322.2.4 Parallel Input and Serial Output (PISO) 322.3 Counters 332.3.1 Synchronous Counter 332.3.2 Asynchronous Counter 332.3.3 Design of a 3-Bit Synchronous Up-counter 342.3.4 Ring Counter 362.3.5 Johnson Counter 372.4 Finite State Machine (FSM) 372.4.1 Mealy and Moore Machine 382.4.2 Pattern or Sequence Detector 38Review Questions 41Multiple Choice Questions 41Reference 423 Introduction to Verilog HDL 433.1 Basics of Verilog HDL 433.1.1 Introduction to VLSI 433.1.2 Analog and Digital VLSI 433.1.3 Machine Language and HDLs 443.1.4 Design Methodologies 443.1.5 Design Flow 453.2 Level of Abstractions and Modeling Concepts 453.2.1 Gate Level 453.2.2 Dataflow Level 473.2.3 Behavioral Level 473.2.4 Switch Level 473.3 Basics (Lexical) Conventions 473.3.1 Comments 473.3.2 Whitespace 483.3.3 Identifiers 483.3.4 Escaped Identifiers 483.3.5 Keywords 483.3.6 Strings 493.3.7 Operators 493.3.8 Numbers 493.4 Data Types 503.4.1 Values 503.4.2 Nets 503.4.3 Registers 513.4.4 Vectors 513.4.5 Integer Data Type 513.4.6 Real Data Type 513.4.7 Time Data Type 523.4.8 Arrays 523.4.9 Memories 523.5 Testbench Concept 53Multiple Choice Questions 53References 544 Programming Techniques in Verilog I 554.1 Programming Techniques in Verilog I 554.2 Gate-Level Model of Circuits 554.3 Combinational Circuits 574.3.1 Adder and Subtractor 574.3.2 Multiplexer and De-multiplexer 664.3.3 Decoder and Encoder 714.3.4 Comparator 75Review Questions 77Multiple Choice Questions 77References 785 Programming Techniques in Verilog II 795.1 Programming Techniques in Verilog II 795.2 Dataflow Model of Circuits 795.3 Dataflow Model of Combinational Circuits 805.3.1 Adder and Subtractor 805.3.2 Multiplexer 825.3.3 Decoder 855.3.4 Comparator 865.4 Testbench 875.4.1 Dataflow Model of the Half Adder and Testbench 885.4.2 Dataflow Model of the Half Subtractor and Testbench 895.4.3 Dataflow Model of 2 × 1 Mux and Testbench 905.4.4 Dataflow Model of 4 × 1 Mux and Testbench 915.4.5 Dataflow Model of 2-to-4 Decoder and Testbench 92Review Questions 93Multiple Choice Questions 94References 956 Programming Techniques in Verilog II 976.1 Programming Techniques in Verilog II 976.2 Behavioral Model of Combinational Circuits 986.2.1 Behavioral Code of a Half Adder Using If-else 986.2.2 Behavioral Code of a Full Adder Using Half Adders 996.2.3 Behavioral Code of a 4-bit Full Adder (FA) 1006.2.4 Behavioral Model of Multiplexer Circuits 1016.2.5 Behavioral Model of a 2-to-4 Decoder 1046.2.6 Behavioral Model of a 4-to-2 Encoder 1066.3 Behavioral Model of Sequential Circuits 1086.3.1 Behavioral Modeling of the D-Latch 1086.3.2 Behavioral Modeling of the D-F/F 1096.3.3 Behavioral Modeling of the J-K F/F 1106.3.4 Behavioral Modeling of the D-F/F Using J-K F/F 1126.3.5 Behavioral Modeling of the T-F/F Using J-K F/F 1136.3.6 Behavior Modeling of an S-R F/F Using J-K F/F 114Review Questions 115Multiple Choice Questions 115References 1167 Digital Design Using Switches 1177.1 Switch-Level Model 1177.2 Digital Design Using CMOS Technology 1187.3 CMOS Inverter 1197.4 Design and Implementation of the Combinational Circuit Using Switches 1207.4.1 Types of Switches 1207.4.2 CMOS Switches 1217.4.3 Resistive Switches 1217.4.4 Bidirectional Switches 1227.4.5 Supply and Ground Requirements 1227.5 Logic Implementation Using Switches 1237.5.1 Digital Design with a Transmission Gate 1277.6 Implementation with Bidirectional Switches 1277.6.1 Multiplexer Using Switches 1277.7 Verilog Switch-Level Description with Structural-Level Modeling 1317.8 Delay Model with Switches 131Review Questions 132Multiple Choice Questions 133References 1348 Advance Verilog Topics 1358.1 Delay Modeling and Programming 1358.1.1 Delay Modeling 1358.1.2 Distributed-Delay Model 1358.1.3 Lumped-Delay Model 1368.1.4 Pin-to-Pin-Delay Model 1378.2 User-Defined Primitive (UDP) 1388.2.1 Combinational UDPs 1398.2.2 Sequential UDPs 1428.2.3 Shorthands in UDP 1448.3 Task and Function 1448.3.1 Difference between Task and Function 1448.3.2 Syntax of Task and Function Declaration 1458.3.3 Invoking Task and Function 1478.3.4 Examples of Task Declaration and Invocation 1478.3.5 Examples of Function Declaration and Invocation 148Review Questions 148Multiple Choice Questions 149References 1499 Programmable and Reconfigurable Devices 1519.1 Logic Synthesis 1519.1.1 Technology Mapping 1519.1.2 Technology Libraries 1529.2 Introduction of a Programmable Logic Device 1529.2.1 PROM, PAL and PLA 1539.2.2 SPLD and CPLD 1549.3 Field-Programmable Gate Array 1569.3.1 FPGA Architecture 1589.4 Shannon's Expansion and Look-up Table 1589.4.1 2-Input LUT 1599.4.2 3-Input LUT 1609.5 FPGA Families 1619.6 Programming with FPGA 1619.6.1 Introduction to Xilinx Vivado Design Suite for FPGA-Based Implementations 1639.7 ASIC and Its Applications 163Review Questions 164Multiple Choice Questions 164References 16710 Project Based on Verilog HDLs 16910.1 Project Based on Combinational Circuit Design Using Verilog HDL 17110.1.1 Full Adder Using Switches at Structural Level Model 17110.1.2 Ripple-Carry Full Adder (RCFA) 17410.1.3 4-bit Carry Look-ahead Adder (CLA) 17410.1.4 Design of a 4-bit Carry Save Adder (CSA) 17610.1.5 2-bit Array Multiplier 17710.1.6 2 × 2 Bit Division Circuit Design 17810.1.7 2-bit Comparator 17910.1.8 16-bit Arithmetic Logic Unit 18010.1.9 Design and Implementation of 4 × 16 Decoder Using 2 × 4 Decoder 18110.2 Project Based on Sequential Circuit Design Using Verilog HDL 18210.2.1 Design of 4-bit Up/down Counter 18210.2.2 LFSR Based 8-bit Test Pattern Generator 18310.3 Counter Design 18510.3.1 Random Counter that Counts Sequence like 2,4,6,8,2,8...and so On 18510.3.2 Use of Task at the Behavioral-Level Model 18710.3.3 Traffic Signal Light Controller 18810.3.4 Hamming Code(h,k) Encoder/Decoder 189Review Questions 192Multiple Choice Questions 192References 19311 System Verilog 19511.1 Introduction 19511.2 Distinct Features of System Verilog 19511.2.1 Data Types 19611.2.2 Arrays 19711.2.3 Typedef 19911.2.4 Enum 20011.3 Always_type 20111.4 $log2c() Function 20211.5 System-Verilog as a Verification Language 203Review Questions 203Multiple Choice Questions 204Reference 204Index 205

O autorze

Suman Lata Tripathi is Professor of VLSI Design at Lovely Professional University, India. She is a senior member of the IEEE and received her PhD in microelectronics and VLSI Design from Motilal Nehru National Institute of Technology, Allahabad, India.Sobhit Saxena is Associate Professor of VLSI Design at Lovely Professional University, India. He received his PhD from IIT Roorkee, India.Sanjeet K. Sinha, PhD, is Associate Professor of VLSI Design at Lovely Professional University, India. He received his PhD from the National Institute of Technology, Silchar, India.Govind S. Patel, PhD, is Professor of VLSI Design at IIMT College of Engineering, Greater Noida, UP, India. He received his doctorate from Thapar University in Patiala, India.