Digital Systems Design with VHDL and Synthesis: An Integrated Approach

ISBN-13: 9780769500232 / Angielski / Twarda / 1999 / 518 str.

Kou-Chuan Chang; K. C. Chang

Opis

K.C. Chang presents an integrated approach to digital design principles, processes, and implementations to help the reader design increasingly complex systems within shorter design cycles. Chang introduces digital design concepts, VHDL coding, VHDL simulation, synthesis commands, and strategies together. Digital Systems Design with VHDL and Synthesis focuses on the ultimate product of the design cycle: the implementation of a digital design. Many of the design techniques and considerations illustrated in the text are examples of actual real-world designs. Unique features of the book include the following:

• VHDL code explained line by line to capture the logic behind the design concepts
• Simulation waveforms, synthesized schematics, and results are shown, verified, and analyzed
• VHDL code is synthesized and commands and strategies are discussed
• Variations on the design techniques and common mistakes are addressed
• Demonstrated standard cell, gate array, and FPGA three design processes, each with a complete design case study
• Test bench, post-layout verification, and test vector generation processes are illustrated

Spis treści

Chapter 1: Introduction.

Chapter 2: VHDL and Digital Circuit Primitives.

Chapter 3: VHDL Simulation and Synthesis Environment and Design Process.

Chapter 4: Basic Combinational Circuits.

Chapter 5: Basic Binary Arithmetic Circuits.

Chapter 6: Basic Sequential Circuits.

Chapter 7: Registers.

Chapter 8: Clock and Reset Circuits.

Chapter 9: Dual–Port RAM, FIFO, and DRAM Modeling.

Chapter 10: A Design Case Study: Finite Impulse Response Filter ASIC Design.

Chapter 11: A Design Case Study: A Microprogram Controller Design.

Chapter 12: Error Detection and Correction.

Chapter 13: Fixed–Point Multiplication.

Chapter 14: Fixed–Point Division.

Chapter 15: Floating–Point Arithmetic.

Appendix A: Package Pack.

Index.