Designing Network On-Chip Architectures in the Nanoscale Era

ISBN-13: 9781439837108 / Angielski / Twarda / 2010 / 528 str.

Jose Flich Cardo;Davide Bertozzi;?Abar

Opis

Paving the way for the use of network on-chip architectures in 2015 platforms, this book presents the industrial requirements for such long-term platforms as well as the main research findings for technology-aware architecture design. It covers homogeneous design techniques and guidelines, including the solutions that are most appealing to the industry and best suited to meet the requirements of on-chip integration. Each chapter deals with a specific key architecture design, including fault tolerant design, topology selection, dynamic voltage and frequency scaling, synchronization, network on-chip resources exposed to the architecture, routing algorithms, and collective communication.

Spis treści

NoC Technology. The Industrial Perspective. Upcoming Trends. Appendix. Bibliography.

O autorze

José Flich is an associate professor of computer architecture and technology at the Technical University of Valencia. Dr. Flich is the coordinator of the EU-funded NaNoC project; co-chair of the CAC, CASS, and INA-OCMC workshops; and co-developer of RECN, the only truly scalable congestion management technique proposed to date. He is also associate editor of the IEEE Transactions on Parallel and Distributed Systems. His research interests include high-performance interconnection networks for multiprocessor systems, clusters of workstations, and networks on-chip.

Davide Bertozzi is an assistant professor and leader of the Multi-Processor Systems-On-Chip research group at the University of Ferrara. Dr. Bertozzi is the general chair of the INA-OCMC workshop and an editorial board member of IET Computers & Digital Techniques. His research interests encompass multi-core digital integrated systems, with an emphasis on all aspects of system interconnect design.