Designing CMOS Circuits for Low Power

ISBN-13: 9781441953148 / Angielski / Miękka / 2010 / 277 str.

Dimitrios Soudris; Christian Piguet; Costas Goutis

Opis

This book is the fourth in a series on novel low power design architectures, methods and design practices. It results from of a large European project started in 1997, whose goal is to promote the further development and the faster and wider industrial use of advanced design methods for reducing the power con- sumption of electronic systems. Low power design became crucial with the wide spread of portable infor- mation and communication terminals, where a small battery has to last for a long period. High performance electronics, in addition, suffers from a per- manent increase of the dissipated power per square millimeter of silicon, due to the increasing clock-rates, which causes cooling and reliability problems or otherwise limits the performance. The European Union's Information Technologies Programme 'Esprit' did therefore launch a 'Pilot action for Low Power Design', which eventually grew to 19 R&D projects and one coordination project, with an overall budget of 14 million EURO. It is meanwhile known as European Low Power Initiative for Electronic System Design (ESD-LPD) and will be completed in the year 2002. It involves to develop or demonstrate new design methods for power reduction, while the coordination project takes care that the methods, experiences and results are properly documented and publicised.

Spis treści

List of Figures. List of Tables. Contributing Authors. Foreword. Introduction. Part I: Low Power Design Methods. 1. Motivation, Context and Objectives; D. Soudris, C. Piguet, C. Goutis. 2. Sources of power dissipation in CMOS circuits; D. Soudris, A. Thanailakis. 3. Logic Level Power Optimization; G. Theodoridis, D. Soudris. 4. Circuit-Level Low-Power Design; S. Nikolaidis, A. Chatzigeorgiou. 5. Circuit Techniques for Reducing Power Consumption in Adders and Multipliers; L. Bisdounis, D. Gouvetas, O. Koufopavlou. 6. Computer Arithmetic Techniques for Low-Power Systems; V. Paliouras, T. Stouraitis. 7. Reducing Power Consumption in Memories; A. Chatzigeorgiou, S. Nikolaidis. 8. Low-Power Clock, Interconnect and Layout Designs; C. Piguet. 9. Logic Level Power Estimation; G. Theodoridis, C. Goutis. Part II: Low Power Design Stories. 10. Low-Power Design for Safety-Critical Applications; A. Kakarountas, K. Papadomanolakis, C. Goutis. 11. Design of a Low Power Ultrasound Beamformer ASIC; R. Schwann, T. Heselhaus, O. Weiss, T.G. Noll. 12. Epilogue; C. Piguet. Index.