Design of VLSI Circuits: Based on Venus

ISBN-13: 9783642955273 / Angielski / Miękka / 2012 / 318 str.

Egon H. Rbst; Christian M. Ller-Schloer; Heinz Schw Rtzel

Opis

Microelectronics are certainly one of the key-technologies of our time. They are a key factor of technological and economic progress. They effect the fields of automation, information and communication, leading to the development of new applications and markets. Attention should be focused on three areas of development: - process and production technology, - test technology, - design technology. Clearly, because of the development of new application fields, the skill f design- ing integrated circuits should not be limited to a few, highly specialized experts Rather, this ability should be made available to all system aDd design engineers as a new application technology - just like nrogramrning technology for software. For this reason, design procedures havt: to be developed which, supported by appropriate CAD systems, provide the desIgn englIl I' with tools for representaltop effective instruments for design and reliable -tools for verificatibn, ensuring simpre, proper and easily controllable interfaces for the manufacturing and test processes. Such CAD systems are called standard design systems. They open the way to fast and safe design of integrated circuits. First, this book demonstrates basic principles with an example of the Siemens design system VENUS, gives a general introduction to the method of designing integrated circuits, familiarizes the reader with basic semiconductor and circuit tech- nologies, shows the various methods of layout design, and presents necessary con- cepts and strategies of test technology.

Spis treści

1 Introduction to the Design of Integrated Circuits.- 1.1 User Technology for Digital Electronics.- 1.2 The Process of Problem Solving.- 1.2.1 Phase Model of the Problem Solving Process.- 1.2.2 CAD Tools Used for the Process of Problem Solving.- 1.3 Procedure Example ADUS.- 1.4 HW Method Versus SW Method.- 1.4.1 Design Levels.- 1.4.2 Verification Procedure.- 1.4.3 Test Preparation.- 1.4.4 Production.- 1.5 The IC Design Process as Problem Solving Process.- 1.5.1 General IC design Process.- 1.5.2 Models and Libraries.- 1.5.3 Technology Dependence.- 1.5.4 Verification.- 1.5.5 Standard IC Design Procedure.- 1.6 Introduction to the Standard Methods of the Layout Design.- 1.6.1 Cell Scheme.- 1.6.2 Arrangement and Connection Scheme.- 1.6.3 Application Scheme.- 1.6.4 Compatibility.- 1.6.5 User-Specific Definition of ICs and Cells: Review of Terminology.- 1.7 Interpretations of the Terminology.- Literature-Chapter 1.- 2 Introduction to Semiconductor Technology for Integrated Circuits.- 2.1 Summary.- 2.2 Components and Technology.- 2.2.1 The Bipolar Transistor.- 2.2.2 The MOS Transistor.- 2.3 Bipolar Semiconductor Circuits.- 2.3.1 Bipolar Logic Circuits.- 2.3.2 Bipolar Memories.- 2.4 MOS Semiconductor Circuits.- 2.4.1 MOS Logic Circuits.- 2.4.2 MOS Semiconductor Memory.- 2.5 Analog MOS Circuits.- 2.5.1 Analog Cells.- 2.5.2 Analog-Digital-Mix.- 2.6 Mounting and Packaging.- Literature-Chapter 2.- 3 Layout Design Methods.- 3.1 Cell-Oriented Design Methods.- 3.1.1 Standard Design Methods Using Libraries.- 3.1.2 Placement and Routing Procedures.- 3.2 The Gate-Array Design Method.- 3.2.1 Basic Cells and their Arrangement on the Master.- 3.2.2 Placement and Routing of a Gate-Array Design.- 3.2.3 ECL Gate-Arrays.- 3.3 Cell-Oriented Design Methods without Préfabrication.- 3.4 Standard Cells.- 3.4.1 Defining Standard Cells.- 3.4.2 Placement and Routing of a Standard Cell Design.- 3.5 Macrocells.- 3.5.1 Design of Macrocells.- 3.5.2 Hierarchical Design.- 3.5.3 Placement and Routing of a Macrocell Design.- 3.6 User-Specific Cells.- 3.6.1 Simple Parameterizable Cells.- 3.6.2 Functionally Parameterizable Cells.- 3.7 Free Macrocells and Manual Layout.- 3.7.1 Manual Layout.- 3.7.2 Geometric Design Rules.- 3.7.3 Regular Design.- 3.7.4 Symbolic Layout.- 3.7.5 Layout According to the Gate-Matrix Method.- 3.8 Distinctive Features of the Layout with Analog Cells.- Literature-Chapter 3.- 4 Test Concepts.- 4.1 Introduction to the Problem of Testing.- 4.1.1 Test Strategy.- 4.1.2 Faults, Error, Failure, and Fault Models.- 4.1.3 Phases of Test Technology in the IC Design Process.- 4.2 Design for Testability.- 4.2.1 Design Utilizing Test Design Rules.- 4.2.2 Ad-Hoc Techniques.- 4.2.3 Structured Methods.- 4.2.3.1 Scan-Path.- 4.2.3.2 Random-Access Scan.- 4.2.4 Design for Testability with VENUS.- 4.3 Tools for the Design for Testability.- 4.3.1 Testability Analysis with VENUS.- 4.3.2 Test Rule Check with VENUS.- 4.4 Test Data Generation.- 4.4.1 Generation of the Input Stimuli.- 4.4.2 Generation and Evaluation of the Test Patterns.- 4.4.3 Test Program Generation.- 4.4.4 Test Preparation with VENUS.- 4.5 Tools for Testing.- 4.5.1 Wafer Prober.- 4.5.2 Electron Beam Prober.- 4.5.3 Automatic Test Equipment (ATE).- 4.6 Selftest.- 4.6.1 Stimuli Generators.- 4.6.2 Test Response Evaluator.- Literature-Chapter 4.- 5 Cells and Libraries.- 5.1 Application of Cell Libraries.- 5.1.1 Functional Scope.- 5.1.1.1 CMOS Libraries.- 5.1.1.2 ECL Library.- 5.1.2 Structure of the Data Sheets.- 5.1.3 Excerpt from the Cell Catalogs of the A/B-Families.- 5.1.4 Data Sheet G-Family.- 5.1.5 Data Sheets of the K- and F-Families.- 5.1.6 Data Sheet Z-Family.- 5.2 Development of the Cell Libraries.- 5.2.1 Objectives and Cell Concept.- 5.2.2 Design of Model Libraries.- 5.2.3 Development Procedure.- 5.2.4 Distinctive Features of the Development of User-Specified Cells.- 5.2.5 Quality Assurance.- 5.2.6 Quality Standard.- Literature-Chapter 5.- 6 Application of the VENUS Design System.- 6.1 Summary.- 6.2 Customer/Manufacturer Interfaces.- 6.3 Organisational Preparation of the VENUS Application.- 6.4 Technical Preparation for VENUS Application.- 6.5 Design Steps of Computer-Aided Circuit Design with VENUS.- 6.5.1 Selection of Cell Library and Master.- 6.5.2 System Initialization.- 6.5.3 Schematic Entry on a Graphic Terminal of a Work Station.- 6.5.4 Net List Transfer to the Mainframe, Set-up of the Project Data Base.- 6.5.5 Logic Verification.- 6.5.6 Testability Analysis.- 6.5.7 Chip Design.- 6.5.8 Layout Analysis and Resimulation.- 6.5.9 Production Data Generation.- 6.5.10 Test Data Generation.- 6.6 Sample Fabrication.- 6.7 Test.- Literature-Chapter 6.- 7 Outlook.- 7.1 Functional Scope.- 7.2 Aspects of Wide-Scope Application.- 7.3 Embedding in the System Design.- 7.4 Embedding in the Technology Development.- Literature-Chapter 7.