Design Of High Speed and Low Power Multiplier

ISBN-13: 9786139461349 / Angielski / Miękka / 2019 / 56 str.

S. Gopalakrishnan; G. Sasi

Opis

Power dissipation is recognized as a critical parameter in modern VLSI field. To produce consumer electronics goods with more backup and less weight, low power VLSI design is necessary.The increasing speed and complexity of today's designs implies a significant increase in the power consumption of very-large-scale integration (VLSI) chips. Multiplication is an important part of real-time digital signal processing (DSP) applications ranging from digital filtering to image processing.The Spurious Power Suppression Technique (SPST) uses a detection logic circuit to detect the effective data range of arithmetic units.

O autorze

Gopalakrishnan, S.
Dr.S.Gopalakrishnan, M.E, Ph.D.,Assistant Professor,Department of ECE,CMR College of Engineering &Technology, Hyderabad.Telangana-501401,India. Mrs.G.Sasi,B.E,M.E.,Assistant Professor,Department of ECE,PSNA College of Engineering &Technology,Dindigul, Tamilnadu-624622, India